Rainbow Electronics HT49R70A-1 - Manual (Page 19)

HT49R70A-1
Rev. 1.00 19 December 4, 2001
Input/output ports
There are two 8-bit bidirectional input/output ports, PA
and PC and one 8-bit input port PB. PA, PB and PC are
mapped to [12H], [14H] and [16H] of the RAM, respec-
tively. PA0~PA3 can be configured as CMOS (output) or
NMOS (input/output) with or without pull-high resistor by
options. PA4~PA7 are always pull-high and NMOS (in-
put/output). If NMOS (input) is chosen, each bit on the
port (PA0~PA7) can be configured as a wake-up input.
PB can only be used for input operation. PC can be con-
figured as CMOS output or NMOS input/output with or
without pull-high resistor by options. All the ports for the
input operation (PA, PB and PC), are non-latched, that
is, the inputs should be ready at the T2 rising edge of the
instruction MOV A, [m] (m=12H or 14H or 16H). For PA,
PC output operation, all data are latched and remain un-
changed until the output latch is rewritten.
When the PA and PC structures are open drain NMOS
type, it should be noted that, before reading data from
the pads, a ²1² should be written to the related bits to
disable the NMOS device. That is, executing first the in-
struction ²SET [m].i² (i=0~7 for PA) to disable related
NMOS device, and then ²MOV A, [m]² to get stable data.
After chip reset, these input lines remain at the high level
or are left floating (by options). Each bit of these output
latches can be set or cleared by the ²MOV [m], A²
(m=12H or 16H) instruction.
Some instructions first input data and then follow the
output operations. For example, ²SET [m].i², ²CLR
[m].i ², ²CPL [m]², ²CPLA [m]² read the entire port states
into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or to the accumulator. When a PA or PC line is
used as an I/O line, the related PA or PC line options
should be configured as NMOS with or without pull-high
resistor. Once a PA or PC line is selected as a CMOS
output, the I/O function cannot be used.
The input state of a PA or PC line is read from the related
PA or PC pad. When the PA or PC is configured as
NMOS with or without pull-high resistor, one should be
careful when applying a read-modify-write instruction to
PA or PC. Since the read-modify-write will read the en-
tire port state (pads state) first, execute the specified in-
struction and then write the result to the port data
register. When the read operation is executed, a fault
pad state (caused by the load effect or floating state)
may be read. Errors will then occur.
There are three function pins that share with the PA port:
PA0/BZ, PA1/BZ and PA3/PFD.
The BZ and BZ are buzzer driving output pair and the
PFD is a programmable frequency divider output. If the
user wants to use the BZ/BZ or PFD function, the related
PA port should be set as a CMOS output. The buzzer
output signals are controlled by PA0 and PA1 data regis-
ters as defined in the following table.
PA1 Data
Register
PA0 Data
Register
PA0/PA1 Pad State
0 0 PA0=BZ, PA1=BZ
1 0 PA0=BZ, PA1=0
X 1 PA0=0, PA1=0
Note: ²X² stands for ²unused²
The PFD output signal function is controlled by the PA3
data register and the timer/event counter state. The
PFD output signal frequency is also dependent on the
timer/event counter overflow period. The definitions of
PFD control signal and PFD output frequency are listed
in the following table.
Timer
Timer
Preload
Value
PA3 Data
Register
PA3
Pad
State
PFD Fre-
quency
OFF X 0 U X
OFF X 1 0 X
ON N 0 PFD
f
INT
/
[2 ´(256-N)]
ON N 1 0 X
Note: ²X² stands for ²unused²
²U² stands for ²unknown²
²256² is for TMR0. If using TMR1 to generate
PFD, the number should be
²65536².