Rainbow Electronics HT49R70A-1 - Manual (Page 9)

HT49R70A-1
Rev. 1.00 9 December 4, 2001
Stack register - STACK
The stack register is a special part of the memory used
to save the contents of the PC. The stack is organized
into 8 levels and is neither part of the data nor part of the
program, and is neither readable nor writeable. Its acti-
vated level is indexed by a stack pointer (SP) and is nei-
ther readable nor writeable. At the start of a subroutine
call or an interrupt acknowledgment, the contents of the
PC is pushed onto the stack. At the end of the subrou-
tine or interrupt routine, signaled by a return instruction
(RET or ), the contents of the PC is restored to its previ-
ous value from the stack. After chip reset, the SP will
point to the top of the stack.
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag is recorded but the ac-
knowledgment is still inhibited. Once the SP is decre-
mented (by RET or RETI), the interrupt is serviced. This
feature prevents stack overflow, allowing the program-
mer to use the structure easily. Likewise, if the stack is
full, and a ²CALL² is subsequently executed, a stack
overflow occurs and the first entry is lost (only the most
recent six return addresses are stored).
Data memory - RAM
The data memory (RAM) is designed with 245 ´8 bits,
and is divided into two functional groups, namely; spe-
cial function registers and general purpose data mem-
ory, most of which are readable/writeable, although
some are read only.
Of the two types of functional groups, the special func-
tion registers consist of an Indirect addressing register 0
(00H), a Memory pointer register 0 (MP0;01H), an Indi-
rect addressing register 1 (02H), a Memory pointer reg-
ister 1 (MP1;03H), a Bank pointer (BP;04H), an
A c c u m u l a t o r ( A C C ; 0 5 H ) , a P r o g r a m c o u n t e r
lower-order byte register (PCL;06H), a Table pointer
(TBLP;07H), a Table higher-order byte register
(TBLH;08H), a Real time clock control register
(RTCC;09H), a Status register (STATUS;0AH), an Inter-
rupt control register 0 (INTC0;0BH), a Timer/Event
Counter 0 (TMR0;0DH), a Timer/Event Counter 0 con-
trol register (TMR0C;0EH), a Timer/Event Counter 1
(TMR1H:0FH;TMR1L:10H), a Timer/Event Counter 1
control register (TMR1C; 11H), I/O registers (PA;12H,
PB;14H, PC;16H), and Interrupt control register 1
(INTC1;1EH). On the other hand, the general purpose
data memory, addressed from 20H to FFH, is used for
data and control information under instruction com-
mands.
The areas in the RAM can directly handle arithmetic,
logic, increment, decrement, and rotate operations. Ex-
cept some dedicated bits, each bit in the RAM can be
set and reset by ²SET [m].i² and ²CLR [m].i² They are
also indirectly accessible through the Memory pointer
register 0 (MP0;01H) or the Memory pointer register 1
(MP1;03H).
Indirect addressing register
Location 00H and 02H are indirect addressing registers
that are not physically implemented. Any read/write op-
eration of [00H] and [02H] accesses the RAM pointed to
by MP0 (01H) and MP1(03H) respectively. Reading lo-
cation 00H or 02H indirectly returns the result 00H.
While, writing it indirectly leads to no operation.
The function of data movement between two indirect ad-
dressing registers is not supported. The memory pointer
registers, MP0 and MP1, are both 8-bit registers used to
access the RAM by combining corresponding indirect
addressing registers. MP0 can only be applied to data
memory, while MP1 can be applied to data memory and
LCD display memory.
G e n e r a l P u r p o s e
D A T A M E M O R Y
( 2 2 4 B y t e s )
S p e c i a l P u r p o s e
D A T A M E M O R Y
0 0 H
0 1 H
0 2 H
0 3 H
0 4 H
0 5 H
0 6 H
0 7 H
0 8 H
0 9 H
0 A H
0 B H
0 C H
0 D H
0 E H
0 F H
1 0 H
1 1 H
1 2 H
1 3 H
1 4 H
1 5 H
1 6 H
1 7 H
1 8 H
1 9 H
1 A H
1 B H
1 C H
1 D H
1 E H
1 F H
F F H
: U n u s e d .
R e a d a s " 0 "
2 0 H
I N T C 1
M P 0
I n d i r e c t A d d r e s s i n g R e g i s t e r 0
I n d i r e c t A d d r e s s i n g R e g i s t e r 1
M P 1
B P
A C C
P C L
T B L P
T B L H
R T C C
S T A T U S
I N T C 0
T M R 0
T M R 0 C
T M R 1 L
T M R 1 C
P A
P B
P C
T M R 1 H
RAM mapping