Rainbow Electronics HT49R70A-1 - Manual (Page 10)

HT49R70A-1
Rev. 1.00 10 December 4, 2001
Accumulator - ACC
The accumulator (ACC) is related to the ALU opera-
tions. It is also mapped to location 05H of the RAM and
is capable of operating with immediate data. The data
movement between two data memory locations must
pass through the ACC.
Arithmetic and logic unit - ALU
This circuit performs 8-bit arithmetic and logic opera-
tions and provides the following functions:
· Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
· Logic operations (AND, OR, XOR, CPL)
· Rotation (RL, RR, RLC, RRC)
· Increment and Decrement (INC, DEC)
· Branch decision (SZ, SNZ, SIZ, SDZ etc.)
The ALU not only saves the results of a data operation
but also changes the status register.
Status register - STATUS
The status register (0AH) is 8 bits wide and contains, a
carry flag (C), an auxiliary carry flag (AC), a zero flag (Z),
an overflow flag (OV), a power down flag (PD), and a
watchdog time-out flag (TO). It also records the status
information and controls the operation sequence.
Except for the TO and PD flags, bits in the status reg-
ister can be altered by instructions similar to other reg-
isters. Data written into the status register does not alter
the TO or PD flags. Operations related to the status reg-
ister, however, may yield different results from those in-
tended. The TO and PD flags can only be changed by a
Watchdog Timer overflow, chip power-up, or clearing
the Watchdog Timer and executing the ²HALT² instruc-
tion. The Z, OV, AC, and C flags reflect the status of the
latest operations.
On entering the interrupt sequence or executing the
subroutine call, the status register will not be automati-
cally pushed onto the stack. If the contents of the status
is important, and if the subroutine is likely to corrupt the
status register, the programmer should take precautions
and save it properly.
Interrupts
The HT49R70A-1 provides two external interrupts, two
internal timer/event counter interrupts, an internal time
base interrupt, and an internal real time clock interrupt.
The interrupt control register 0 (INTC0;0BH) and inter-
rupt control register 1 (INTC1;1EH) both contain the in-
t e r r u p t c o n t r o l b i t s t h a t a r e u s e d t o s e t t h e
enable/disable status and interrupt request flags.
Once an interrupt subroutine is serviced, other inter-
rupts are all blocked (by clearing the EMI bit). This
scheme may prevent any further interrupt nesting.
Other interrupt requests may take place during this in-
terval, but only the interrupt request flag will be re-
corded. If a certain interrupt requires servicing within the
service routine, the EMI bit and the corresponding bit of
the INTC0 or of INTC1 may be set in order to allow in-
terrupt nesting. Once the stack is full, the interrupt re-
quest will not be acknowledged, even if the related
interrupt is enabled, until the SP is decremented. If im-
mediate service is desired, the stack should be pre-
vented from becoming full.
All these interrupts can support a wake-up function. As
an interrupt is serviced, a control transfer occurs by
pushing the contents of the PC onto the stack followed
by a branch to a subroutine at the specified location in
the ROM. Only the contents of the PC is pushed onto
the stack. If the contents of the register or of the status
register (STATUS) is altered by the interrupt service pro-
Labels Bits Function
C 0
C is set if the operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate
through carry instruction.
AC 1
AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from
the high nibble into the low nibble in subtraction; otherwise AC is cleared.
Z 2 Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.
OV 3
OV is set if the operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
PD 4
PD is cleared by either a system power-up or executing the ²CLR WDT² instruction. PD is set
by executing the ²HALT² instruction.
TO 5
TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO is
set by a WDT time-out.
¾ 6 Unused bit, read as ²0²
¾ 7 Unused bit, read as ²0²
Status register