Rainbow Electronics AT84AD004 - Manual (Page 12)

12
AT84AD004
5390A–BDC–06/04
Timing Diagrams
Figure 4. Timing Diagram, ADC I or ADC Q, 1:2 DMUX Mode, Clock I for ADC I, Clock Q for ADC Q
Figure 5. 1:1 DMUX Mode, Clock I = ADC I, Clock Q = ADC Q
CLKOI or CLKOQ
(= CLKI/4)
CLKI or CLKQ
CLKOI or CLKOQ
(= CLKI/2)
Programmable delay
VIN
TA
N
N + 1
N + 2
N + 3
Pipeline delay = 4 clock cycles TDO
TD2
DOIA[0:7]
or DOQA[0:7]
N - 2 N - 4 N
DOIB[0:7]
or DOQB[0:7]
Pipeline delay = 3 clock cycles TDO
N - 3 N - 1 N +1
Address: D7 D6 D5 D4 D3 D2 D1 D0
1 1 X X 1 X 0 0
CLKI or CLKQ
CLKOI or CLKOQ
VIN
TA
N
N + 1
N + 2
N + 3
Pipeline delay = 3.5 clock cycles TDO
DOIA[0:7]
or DOQA[0:7] N - 1 N - 3 N + 1 N - 2 N
DOIB[0:7] and DOQB[0:7] are high impedance
Address: D7 D6 D5 D4 D3 D2 D1 D0
1 1 X X 0 X 0 0