Rainbow Electronics AT84AD001B - Manual (Page 15)

15
AT84AD001B
2153C–BDC–04/04
Figure 8. 1:2 DMUX Mode, Clock I = ADC I, Clock IN = ADC Q
CLKI
CLKOI
(= CLKI/2)
VIN
TA
N
N + 1
N + 4
N + 6
Pipeline delay = 4 clock cycles TDO
TD2
DOQA[0:7]
N - 4 N - 8 N
DOQB[0:7]
Pipeline delay = 3 clock cycles
TDO
N - 6 N - 2 N + 2
Address: D7 D6 D5 D4 D3 D2 D1 D0
0 X X X 1 X 0 0
N - 7 N - 3 N + 1
N - 5 N - 1 N + 3
DOIA[0:7]
DOIB[0:7]
CLKOQ is high impedance
CLKIN
Pipeline delay = 3.5 clock cycles
TDO
N + 2
N + 3
N + 5
CLKOI
(= CLKI/4)