Rainbow Electronics AT84AD001B - Manual (Page 54)

54
AT84AD001B
2153C–BDC–04/04
Figure 60. Example of Termination for Channel I Used in DMUX 1:1 Ratio (Port B Unused)
Note: If the outputs are to be used in single-ended mode, it is recommended that the true and false signals be terminated with a 50
Ω
resistor.
Using the Dual ADC With
and ASIC/FPGA Load Figure 61 on page 55 illustrates the configuration of the dual ADC (1:2 DMUX mode,
independent I and Q clocks) driving an LVDS system (ASIC/FPGA) with potential addi-
tional DMUXes used to halve the speed of the dual ADC outputs.
Port B
DOBI0 / DOBI0N
DOBI1 / DOBI1N
DOBI2 / DOBI2N
DOBI3 / DOBI3N
DOBI4 / DOBI4N
DOBI5 / DOBI5N
DOBI6 / DOBI6N
DOBI7 / DOBI7N
Floating (High Z)
Port A
DOAI0 / DOAI0N
DOAI1 / DOAI1N
DOAI2 / DOAI2N
DOAI3 / DOAI3N
DOAI4 / DOAI4N
DOAI5 / DOAI5N
DOAI6 / DOAI6N
DOAI7 / DOAI7N
VCCO
DOAI0
DOAI0N
Z0 = 50
Ω
Z0 = 50
Ω
100
Ω
LVDS In
LVDS In
Dual ADC Package