Rainbow Electronics AT84AD001B - Manual (Page 16)

16
AT84AD001B
2153C–BDC–04/04
Figure 9. 1:1 DMUX Mode, Clock I = ADC I, Clock IN = ADC Q
Figure 10. 1:1 DMUX Mode, Decimation Mode Test (1:16 Factor)
Notes: 1. The maximum clock input frequency in decimation mode is 750 Msps.
2. Frequency(CLKOI) = Frequency(Data) = Frequency(CLKI)/16.
CLKI
CLKOI
(= CLKI/2)
VIN
TA
N
N + 1
N + 4
N + 6
Pipeline delay = 3.5 clock cycles TDO
DOQA[0:7]
Address: D7 D6 D5 D4 D3 D2 D1 D0
0 X X X 0 X 0 0
DOIA[0:7]
DOIB[0:7] and DOQB[0:7] are high impedance
CLKOQ is high impedance
CLKIN
N + 2
N + 3
N + 5
N - 2 N - 6 N + 2 N - 4 N
N - 1 N - 5 N + 3 N - 3 N + 1
Pipeline delay = 3 clock cycles
TDO
VIN
N - 16
N
N + 16
N + 32
CLKI
16 clock cycles
CLKOI
DOIA[0:7] N + 16 N + 32 N + 48 N - 16 N
DOQA[0:7]
N + 16 N + 32 N + 48 N - 16 N
Address: D7 D6 D5 D4 D3 D2 D1 D0
1 0 X X 0 X 0 0
DOIB[0:7] and DOQB[0:7] are high impedance
CLKOQ is high impedance