Rainbow Electronics DS2152 - Manual (Page 44)

DS2152
031897 44/79
Performance Report Messages (PRM) as described in
ANSI T1.403 and the messages as described in AT&T
TR54016. The HDLC controller automatically gener-
ates and detects flags, generates and checks the CRC
check sum, generates and detects abort sequences,
stuffs and destuffs zeros (for transparency), and byte
aligns to the FDL data stream. The 16–byte buffers in
the HDLC controller are large enough to allow a full
PRM to be received or transmitted without host inter-
vention. The BOC controller will automatically detect incoming BOC sequences and alert the host. When the
BOC ceases, the DS2152 will also alert the host. The
user can set the device up to send any of the possible
6–bit BOC codes.
There are nine registers that the host will use to operate
and control the operation of the HDLC and BOC control-
lers. A brief description of the registers is shown in
Table 11–1.
HDLC/BOC CONTROLLER REGISTER LIST Table 11–1
NAME FUNCTION
FDL Control Register (FDLC)
FDL Status Register (FDLS)
FDL Interrupt Mask Register (FIMR) general control over the HDLC and BOC controllers
key status information for both transmit and receive directions
allows/stops status bits to/from causing an interrupt
Receive PRM Register (RPRM)
Receive BOC Register (RBOC)
Receive FDL FIFO Register (RFFR) status information on receive HDLC controller
status information on receive BOC controller
access to 16–byte HDLC FIFO in receive direction
Transmit PRM Register (TPRM)
Transmit BOC Register (TBOC)
Transmit FDL FIFO Register (TFFR) status information on transmit HDLC controller
enables/disables transmission of BOC codes
access to 16–byte HDLC FIFO in transmit direction
11.1.2 Status Register for the FDL
Four of the HDLC/BOC controller registers (FDLS,
RPRM, RBOC, and TPRM) provide status information.
When a particular event has occurred (or is occuring),
the appropriate bit in one of these four registers will be
set to a one. Some of the bits in these four FDL status
registers are latched and some are real time bits that are
not latched. Section 11.1.4 contains register descrip-
tions that list which bits are latched and which are not.
With the latched bits, when an event occurs and a bit is
set to a one, it will remain set until the user reads that bit.
The bit will be cleared when it is read and it will not be set
again until the event has occurred again. The real time
bits report the current instantaneous conditions that are
occuring and the history of these bits is not latched.
Like the other status registers in the DS2152, the user
will always proceed a read of any of the four registers
with a write. The byte written to the register will inform
the DS2152 which of the latched bits the user wishes to
read and have cleared (the real time bits are not affected
by writing to the status register). The user will write a
byte to one of these registers, with a one in the bit posi-
tions he or she wishes to read and a zero in the bit posi-
tions he or she does not wish to obtain the latest
information on. When a one is written to a bit location,
the read register will be updated with current value and it
will be cleared. When a zero is written to a bit position,
the read register will not be updated and the previous
value will be held. A write to the status and information
registers will be immediately followed by a read of the
same register. The read result should be logically
AND’ed with the mask byte that was just written and this
value should be written back into the same register to
insure that bit does indeed clear. This second write step
is necessary because the alarms and events in the sta-
tus registers occur asynchronously in respect to their
access via the parallel port. This write–read–write (for
polled driven access) or write–read (for interrupt driven
access) scheme allows an external microcontroller or
microprocessor to individually poll certain bits without
disturbing the other bits in the register. This operation is
key in controlling the DS2152 with higher–order soft-
ware languages.
Like the SR1 and SR2 status registers, the FDLS regis-
ter has the unique ability to initiate a hardware interrupt
via the INT output pin. Each of the events in the FDLS
can be either masked or unmasked from the interrupt
pin via the FDL Interrupt Mask Register (FIMR). Inter-
rupts will force the INT pin low when the event occurs.
The INT pin will be allowed to return high (if no other