Rainbow Electronics AT73C502 - Manual (Page 12)

AT73C500
12
Output Operations
The data output by AT73C500 can be divided into three
categories: data to external processor, status information
and impulse outputs. AT73C500 reads mode information,
and in mode 3 and 4, also calibration data via external bus.
For the I/O operation, two 8-bit buses are allocated.
The same eight data lines are reserved both for the
impulse outputs and for the processor interface. The sepa-
ration is done with two address pins. When communicating
with the microprocessor, address 1 (pin ADDR1) is acti-
vated (high). Impulses are output combined with a high
level of address 0 (ADDR0). For status information sepa-
rate 8-bit bus is reserved. The table below describes the
use of the two buses of AT73C500.
For status and impulse outputs, external latches are
needed to store the information while buses are used for
other tasks. In most cases, the data bus of AT73C500 and
processor I/O bus can be connected directly with each
other. The data transfer is controlled by handshake signals,
ADDR1, RD/WR, STROBE and BRDY. One of the status
outputs DATRDY (B9, ADDR0) can be used as an interrupt
signal. Interrupt can be also generated from the handshake
lines.
In most meters, only some of the I/O operations of
AT73C500 are needed. If a meter contains a separate pro-
cessor, status outputs of AT73C500 are typically not used
since the processor will anyway track the status information
supplied by AT73C500. Often only one or two of the
impulse outputs are wired to the test LED or electrome-
chanical counter.
Data Transfer to External Microprocessor
The calculation results of AT73C500 are transferred to pro-
cessor via 8-bit parallel bus. During normal operation, the
information transfer is divided into six packages which are
written in 200ms intervals after the calculations over ten
line frequency cycles have been completed. There is a time
interval of one line cycle between each individual data
package. The first four bytes of a package contain synchro-
nization, mode and status information, and the rest 12
bytes are reserved for the actual measurement results. The
contents of the six data packages are as follows:
Data bits Bus Address Mode Usage
B0 - B7 Data Bus ADDR0 Output
Impulse
Outputs
B8 - B15 Status Bus ADDR0 Output
Status
Information
B0 - B7 Data Bus ADDR1
Input/
Output
Processor
Interface
B12 - B14 Status Bus ADDRx Input
Mode
Inputs
Table 1. Package 0
Byte Data Order Meaning
1 Sync LS Single byte Synchronization
2 Sync MS Single byte Synchronization
3 Mode Single byte Mode information
4 Status Single byte Status information
5 REG0 (LS+2) byte Active power, phase 1
6 REG0 MS byte Active power, phase 1
7 REG0 LS byte Active power, phase 1
8 REG0 (LS+1) byte Active power, phase 1
9 REG1 (LS+2) byte Active power, phase 2
10 REG1 MS byte Active power, phase 2
11 REG1 LS byte Active power, phase 2
12 REG1 (LS+1) byte Active power, phase 2
13 REG2 (LS+2) byte Active power, phase 3
14 REG2 MS byte Active power, phase 3
15 REG2 LS byte Active power, phase 3
16 REG2 (LS+1) byte Active power, phase 3