Rainbow Electronics AT73C502 User Manual

Page 15

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AT73C500

15

Content of Sync LS byte is described in the following table.
Bits 3-7 of the Sync LS byte are not used.

The Sync MS byte contains a unique 8-bit data, 80H. It can
be used as a synchronization byte by the external control-
ler.

The mode byte contains the following information:

Figure 10. Meaning of bits in mode byte

The contents of the status byte equals the content of the
external Status bus as described in the section “Status
Information” on page 17.

In the beginning of I/O operation, AT73C500 writes a high
pulse to B9 pin of the Status bus (ADDR0). This pin can be
externally latched to lengthen the pulse over the whole out-
put operation. It can be used to generate a data ready
(DATRDY) interrupt to processor.

Figure 11 shows the timing of one data package. In nomi-
nal conditions, it takes 200 clock cycles to transfer all 16
b yt es . A h ig h p ul s e (D A TRD Y ) i s wri tt en to b i t B 9
(SMBUS1) of Status bus 11 clocks before the first byte is
available and low pulse 12 clocks after the last byte has
been sent.

Table 7. Sync LS Byte

B7 - B3

B2

B1

B0

Data

package

Mode

X X X X X

0

0

0

0

Normal operation,
Data output

X X X X X

0

0

1

1

Normal operation,
Data output

X X X X X

0

1

0

2

Normal operation,
Data output

X X X X X

0

1

1

3

Normal operation,
Data output

X X X X X

1

0

0

4

Normal operation,
Data output

X X X X X

1

0

1

5

Normal operation,

Data output

X X X X X

1

1

0

(none)

DSP waiting for
calibration data

X X X X X

1

1

1

3 and 4

PFAIL active,
billing information
to be transferred

B0

B1

B2

B3

B4

B5

B6

B7

Mode byte

Not used

State of MODE

input pins of the

DSP

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