Rainbow Electronics AT86RF230 - Manual (Page 18)

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AT86RF230
5131A-ZIGB-06/14/06
5.2. Configuration
The initialization of the AT86RF230 prior to using RX-AACK or the TX-ARET mode is similar to initializing the IC
prior to switching to regular RX or TX modes.
RX_AACK_ON mode is enabled after the register bits TRX_CMD in register 0x02 (TRX_STATE) is written using
RX_AACK_ON. The IC is in the RX_AACK_ON mode when the register 0x01 (TRX_STATUS) changes to
RX_AACK_ON or BUSY_RX_AACK. For correct RX_AACK_ON operation, the register bit TX_AUTO_CRC_ON
(register 0x05) must be set to “1”.
Similarly, TX_ARET_ON mode is enabled after the register bits TRX_CMD is written with TX_ARET_ON. The IC is
in the TX_ARET_ON mode after TRX_STATUS changes to TX_ARET_ON or to BUSY_TX_ARET. For correct TX-
ARET operation, the register bit TX_AUTO_CRC_ON (register 0x05) must be set to “1”.
The CSMA/CA algorithm can be configured using the 0x2D (CSMA_SEED_0) and the 0x2E (CSMA_SEED_1)
registers. The MIN_BE register bits sets the minimum back-off exponent (refer to the IEEE 802.15.4 standard), and
the CSMA_SEED_* register bits define a random seed for the back-off-time random-number generator in the
AT86RF230. The register bits MAX_CSMA_RETRIES (register 0x2C) configures how often the transceiver will
retry the CSMA/CA algorithm after a busy channel is initially detected.
Both automatic modes can be exited by writing a new mode command to the register bits TRX_CMD in register
0x02 (TRX_STATE). Polling the 0x01 (TRX_STATUS) register for the new state confirms that the transceiver has
left the automatic mode.
5.3. Extended Operation Mode Description
5.3.1. RX_AACK_ON
In the RX_AACK_ON mode, the transceiver listens for incoming frames.
After detecting a frame start, the transceiver will parse the frame contents for frame type and destination address.
The filtering procedure described in IEEE 802.15.4 will be applied to the frame. Any frames rejected by address
filtering will be discarded. A frame will also be discarded if the CRC is found to be invalid.
Otherwise, the TRX_END interrupt will be raised after the reception of the frame is completed. The controller can
then upload the frame.
The transceiver also detects if an ACK frame needs to be sent. If this is true, the transceiver will automatically send
an ACK frame 12 symbol periods after the end of the received frame. Only ACKs with a cleared data-pending bit
will be transmitted.
No ACK will be sent if no ACK is required.
5.3.2. TX_ARET_ON
In TX_ARET_ON mode, the transceiver executes the CSMA/CA algorithm and transmits a frame downloaded by
the controller. If necessary, it will check for an ACK reply, and signal the result of the transaction by raising a
TRX_END interrupt. After the interrupt, the controller may read the value of the register bits TRAC_STATUS
(register 0x02) to determine whether or not the transaction was successful.
The CSMA/CA transmission transaction is started by pulsing the SLP_TR pin high for at least one microsecond.
The frame data must have already been downloaded. Alternatively, the controller may download the frame data
while the transceiver is transmitting the preamble. In this case, it is the responsibility of the controller to ensure that
the data arrives sufficiently early.
The transceiver executes the un-slotted CSMA/CA algorithm as defined by the IEEE 802.15.4 standard. If a clear
channel is detected during CSMA/CA execution, the transceiver will proceed to transmit the frame. If the CSMA/CA
did not detect a clear channel, the channel access will be retried as often as set by the register bits
MAX_CSMA_RETRIES in register 0x2C (XAH_CTRL). In case that CSMA/CA does not detect a clear channel