Rainbow Electronics AT86RF230 - Manual (Page 26)

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AT86RF230
5131A-ZIGB-06/14/06
The interface is designed to work in synchronous or asynchronous mode. In synchronous mode, the CLKM output
of the transceiver IC is used as the master clock of the controller. The SPI clock can be any integer-divided clock
ratio up to 8 MHz.
Nevertheless, usage of an independent controller clock for an asynchronous interface is possible. In asynchronous
mode, the maximum SPI clock speed is limited to 7.5 MHz. The external CLKM output signal is not required and
can be disabled.
SEL enables the MISO output driver of the AT86RF230. If the driver is disabled, there is no internal pull-up
resistor connected to it. Driving the appropriate signal level must be ensured by the master device or an external
pull-up resistor.
The SPI is a byte-oriented serial interface. All bytes are transferred MSB first. Every SPI transfer starts with
0 SEL = and this signal is asserted low as long as one consecutive SPI access occurs. One consecutive access
includes two or more bytes depending on the access mode described later. If 0 SEL = goes high before the end of
one complete access, the internal bit counter is reset and the transferred data are lost.
Both sides of the interface (master and slave) contain an 8-bit shift register. The master starts the transfer by
asserting
0 SEL = . After the 8-bit shift register is loaded, the master generates eight SPI clocks in order to transfer
the data to the slave, and at the same time the slave transmits one byte to the master shift register. If the master
wants to receive one byte of data it must also transmit one byte to the slave. Every transfer starts with a command
byte. This command byte contains the access mode information as well as additional mode-dependent bits. During
command byte transfer, the AT86RF230 returns a byte containing “0”.
Bit 7 Bit 6
(R/W)
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mode
1 0 Register address [5:0] Short mode (register read access)
1 1 Register address [5:0] Short mode (register write access)
0 0 1 Reserved Frame receive mode
0 1 1 Reserved Frame transmit mode
0 0 0 Reserved SRAM read access mode
0 1 0 Reserved SRAM write access mode
Table 7-1. Interface Access Mode Overview
7.2. Register Access Mode (Short Mode)
The register access mode is a two-byte read/write operation. The first byte contains the control information (mode
identifier bit 7, read/write select bit 6, and a 6-bit address). The second byte contains the read or write data. In this
mode a maximum of 64 consecutive registers can be addressed.
byte 2 byte 1
address[5:0] data[7:0]
R/W
1=write
0=read
1
Figure 7-3. Register Short Mode Access