Rainbow Electronics AT86RF230 - Manual (Page 30)

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AT86RF230
5131A-ZIGB-06/14/06
CLKM
SLP_TR
async timer (controller) elapsed
35 main clock cycles
Figure 7-12. Sleep and Wake-up Initiated by Asynchronous Controller Timer Output
CLKM
SLP_TR
IRQ
transceiver IRQ issued
35 main clock cycles
Figure 7-13. Wake-up Initiated by Transceiver Interrupt
7.7. Interrupt Logic
The AT86RF230 can differentiate between six interrupt events. Each interrupt can be enabled or disabled by
writing the corresponding bit to the interrupt mask register. All six internal interrupt lines are combined via logical
“OR” to one external interrupt line. Internally, each interrupt is stored in a separate bit of the interrupt status
register. If the external interrupt line is set, the controller must first read the interrupt status register to determine the
source of the interrupt. A read access to this register clears the interrupt status register and also the external
interrupt line. The interrupt will not be cleared automatically when the event that caused the IRQ is not valid
anymore. Exception: the PLL_LOCK IRQ will clear the PLL_UNLOCK IRQ and vice versa.
For a detailed description of the interrupt status register, please refer to register 0x0F (IRQ_STATUS).
Note: After a reset signal, all interrupts are enabled. Special settings in the register 0x0E (IRQ_MASK) need to be
renewed.