Teledyne LeCroy SDA II - Manual (Page 12)

Serial Data Analysis II Software
Reference Clock Inputs
The Reference Clock Input(s) section in the Ref. Clock Input dialog lets you define the clock input(s). You
can choose Clock+ Only or Clock+ and Clock- .You can also define the upsample rate (when increasing
the sampling rate of the clock signal).
Crossing Level
The Crossing level section of the Reference Clock Inputs dialog lets you set the voltage level where tim-
ing is measured for the reference clock. The crossing level is set separately for the data and clock (the con-
trols on this dialog are for the clock) and can be either absolute or relative.
You can either set the Absolute crossing level in volts (or watts for an optical signal) directly, or you click
the Find Level button to automatically find the level. The level is found by locating the midpoint between
the highest and lowest clock levels in the current acquisition. When you select the Absolute crossing
level, the crossing time used by both the jitter and eye pattern measurements is determined as the time
at which the clock level crosses the specified threshold. The Relative level is automatically set to the
selected percentage on each acquisition.
Clock Timing
The Clock Timing section of the Ref. Clock Input dialog lets you define a clock slope setting. A clock signal
goes through one complete cycle during each bit interval. The edge timing can be measured relative to
the rising slope, falling slope, or both slopes, of the clock by means of the Clock Slope setting.
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