Teledyne LeCroy SDA III-CompleteLinQ - Manual (Page 22)

SDAIII-CompleteLinQ Software
With each acquisition, the clock recovery algorithm determines the optimal recovered clock. Using this
setting causes statistics to be reset with every sweep, including the population within eye diagrams.
Reference Clock section - Enables positioning of the clock edges relative to the data signal. It shifts the
clock signal relative to the data signal. For convenience, it duplicates controls found elsewhere: the Use
Explicit Clock Ref checkbox (serving the same function as the multiplexer switch on the SDA Framework
dialog) and the Slope, Deskew, and Multiplier fields (also found on the Ref. Clock dialog). The Slope set-
ting (active when using an explicit reference clock) determines whether to use positive, negative, or both
edges of the clock signal as the edges that define the system clocking. Deskew allows you to fine-tune the
skew between the clock and data. Varying the deskew value will have the effect of shifting the eye dia-
gram. .
PLL Setup... section - Sets the type and bandwidth of the digital PLL used in SDAII measurements. The
PLL bandwidth limits the response of the recovered clock to high rate variations in the data rate. For
example,depending on the type of PLL, a PLL bandwidth of 5 MHz will allow the recovered clock to track
frequency variations below approximately half this rate, thereby removing their effect from jitter and eye
pattern measurements. Configure this section to match the behavior of the receiver's PLL.
For step-by-step instructions, see Set Up Clock Recovery .
PLL Setup
The PLL Setup section of the Clock dialog contains the controls to set the type and bandwidth of the dig-
ital PLL used in all SDAIII-CompleteLinQ measurements. The PLL bandwidth limits the response of the
recovered clock to high rate variations in the data rate. Configure this section to match the behavior of
your receiver's PLL.
Example: A PLL bandwidth of 5 MHz allows the recovered clock to track frequency variations below
approximately half the frequency, therefore removing the effect from jitter and eye pattern meas-
urements. The software PLL implemented in SDAIII-CompleteLinQ allows you to choose among several
types of PLL.
The selected PLL is applied to either the data stream under test or the selected clock source (if a Ref-
erence Clock is in use) when the PLL On control is checked. The PLL recovers a reference clock from the
selected source, which is used by all subsequent SDAIII-CompleteLinQ measurements.
BW indep of Data
When this option is checked, the PLL algorithm will keep track of the "local" transition density by tracking
the number of UI between edges, and use this information in addition to the last edge's phase difference
in determining the amount of error to feedback into the control loop. This allows the clock recovery algo-
rithm to track the underlying clock when in the presence of varying transition densities. The result is that
the PLL will implement the configured PLL bandwidth, even if the local transition density varies sig-
nificantly from its average value. Use this setting when you want the clock recovery to model a receiver
that uses a PLL which compensates for varying transition density.
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