Teledyne LeCroy SDA III-CompleteLinQ - Manual (Page 26)

SDAIII-CompleteLinQ Software
Clock Recovery Implementation Using a PLL
As shown in the previous image, the initial output and the output of the digital phase detector are set to
zero. The next time value output is equal to the nominal data rate. This value is fed back to the com-
parator on the far left which compares this time value to the measured time of the next data edge from
the digital phase detector. The difference is the error between the data rate and the recovered clock, and
can also incorporate the measurement of the number of UI's since the last edge (that is, the local tran-
sition density).This difference is filtered and added to the initial base period to then generate the cor-
rected clock period. The filter controls the rate of this correction by scaling the amount of error fed back
to the clock period computation. The choice of filter in SDAII and SDAIII-CompleteLinQ includes a single-
pole infinite impulse response (IIR) low-pass filter (the golden PLL, as defined by FibreChannel), a 1 pole 1
zero filter, and a 2 pole 1 zero filter. The equation of the golden PLL 1 pole filter is:
The value of y
k
is the correction value for the kth iteration of the computation and x
k
is the error
between the kth data edge and the corresponding clock edge. Notice that the current correction factor is
equal to the weighted sum of the current error and all previous correction values. The multiplier value is
set to one in the SDA, and the value of n is the PLL cutoff divisor set from the Golden PLL dialog. The cut-
off frequency is Fd/n, where Fd is the data rate. This filter is related to its analog counterpart through a
design process known as impulse invariance and is only valid for cutoff frequencies much less than the
data rate. For this reason, the minimum PLL cutoff divisor setting is 20 in the SDA.
The factor n determines the number of previous values of the correction value y used in the computation
of the current correction value. This is theoretically infinite; however, there is a practical limit to the
number of past values included.
Set Up Reference Clock
An accurate reference clock is central to the measurements performed by SDAIII-CompleteLinQ. When
the clock is recovered from data, the clock is defined from the locations of the data's crossing points in
time. When a reference clock is used, the clock is defined from the locations of the reference clock's cross-
ing points. Starting with zero, the clock edges are computed at specific time intervals relative to each
other.
Example: A 2.5 GHz clock has edges separated in time by 400 ps. Making a 2.5 GHz clock from a 100 MHz
reference clock requires setting the Multiplier to 25.
Follow these steps to define the crossing points.
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