PNI RM3100 Sensor Suite - Manual (Page 23)

PNI Sensor Corporation Doc 1017252 r03
RM3100 & RM2100 Sensor Suite User Manual Page 22 of 45
After communication between the MagI2C and master device is finished, the SPI bus
can be freed up (SSN pin set HIGH) to communicate with other slave devices while
the MagI2C takes a measurement or is idle.
SCLK (pin 27)
SCLK is a SPI input used to synchronize the data sent in and out through the MISO
and MOSI pins. SCLK is generated by the customer-supplied master device and
should be 1 MHz or less. One byte of data is exchanged over eight clock cycles.
Data is captured by the master device on the rising edge of SCLK. Data is shifted out
and presented to the MagI2C on the MOSI pin on the falling edge of SCLK, except
for the first bit (MSB) which must be present before the first rising edge of SCLK.
MISO (pin 28)
MISO is an SPI output that sends data from the MagI2C to the master device. Data is
transferred most significant bit first and is captured by the master device on the rising
edge of SCLK. The MISO pin is placed in a high impedance state if the MagI2C is
not selected (i.e. if SSN=1).
4.3.3 I
2
C Pins
SDA (pin 1)
The SDA line is a bi-directional line used to send commands to the MagI2C and used
to transmit data from the MagI2C. Data is transferred most significant bit first. All
communication between the host and the MagI2C occurs on this line when
implementing the I2C interface.
SA1 (pin 3)
SA1 represents the second-least significant bit in the MagI2C’s slave address.
Pulling this HIGH represents a ‘1’ and pulling it low represents a ‘0’. Along with pin
28 (bit 0) and the higher 5 bits (0b01000), which are pre-defined in hardware, SA1
establishes the 7-bit slave address of the MagI2C on the I
2
C bus.
SCL (pin 27)
SCL is used to synchronize the data sent in and out through the SDA pin. SCL is
generated by the customer-supplied master device and should be 1 MHz or less. Data
is captured by the master device on the rising edge of SCL. Data is shifted out and
presented to the MagI2C on the SDA pin on the falling edge of SCL, except for the
first bit which must be present before the first rising edge of SCL.