Sa0 (pin 28), 4 spi timing requirements, Spi timing requirements – PNI RM3100 Sensor Suite User Manual

Page 24

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PNI Sensor Corporation

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RM3100 & RM2100 Sensor Suite User Manual

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SA0 (pin 28)

SA0 represents the least significant bit in the MagI2C’s slave address. Pulling this
HIGH represents a ‘1’ and pulling it low represents a ‘0’. Along with pin 3 (bit 1)
and the higher 5 bits (0b01000), which are pre-defined in hardware, SA0 establishes

the 7-bit slave address of the MagI2C on the I

2

C bus.

4.4 SPI Timing Requirements

The MagI2C can act as a slave device on a SPI bus. The SPI interface consists of four

signals, as carried on SCLK, MOSI, MISO, and SSN. The SPI clock, SCLK, should run at

1 MHz or less. Data sent out on MOSI is considered valid while SCLK is HIGH, and data is

in transition when SCLK is LOW. The first byte sent to the MagI2C contains the

Read/Write bit (Write=0) followed by the 7-bit register address. When the register address

byte is received the MagI2C returns the STATUS register contents. Assuming SSN stays

low and SCLK continues, multiple registers can be written to or read from as the MagI2C

will automatically increment to the next register address. The clock polarity when the bus is

idle can either be LOW (CPOL=CPHA=0) or HIGH (CPOL=CPHA=1).

As long as SSN is LOW data can transfer to or from the MagI2C. Generally it is a good idea

to pull SSN to HIGH after a read or write operation has completed such that the SPI bus can

be freed up for other devices. The MagI2C can perform measurements while the SSN line is

HIGH, as this does not involve communication with the master. Pulling the SSN to HIGH

during a data read or write will terminate the transaction.

The timing parameters, defined in Figure 4-5 or Figure 4-6 and specified in Table 4-2, must

be met to ensure reliable communication.

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