PNI RM3000 Sensor Suites - Manual (Page 26)

PNI Sensor Corporation Doc #1015673 r08
RM3000 & RM2000 Sensor Suite User Manual – July 2012 Page 26 of 41
DRDY (Data Ready)
DRDY is used to ensure data is read from the 3D MagIC only when it is available.
After initiating a sensor measurement, DRDY will go HIGH when the measurement
is complete. This signals the host that data is ready to be read. The DRDY pin
should be set LOW prior to initiating a measurement. This is done automatically in
Standard Mode and by toggling the CLEAR pin in Legacy Mode.
Note: If a new command sequence is started before the previous measurement has
completed (before DRDY goes HIGH), the previous command will be overwritten. This will
also stop the measurement cycle. If you try to send a new command during the readout
phase, after DRDY goes HIGH, the command will be ignored until all 16 bits have been
clocked our or the CLEAR pin is set HIGH (then LOW again).
CLEAR (Clear Command Register)
To initiate a clear command in Legacy Mode, the CLEAR pin must be toggled LOW-
HIGH-LOW. CLEAR is usually LOW. CLEAR will reset the DRDY pin to LOW.
CLEAR can be used to stop any sensor measurement in progress. CLEAR has no
effect on the SPI register state.
Note: The CLEAR pin is similar to the RESET pin on PNI’s legacy ASIC. However in
Standard Mode the 3D MagIC automatically resets the DRDY line, so it is not necessary to
use the CLEAR pin when operating in Standard Mode.
AVDD and DVDD (Supply Voltages)
AVDD and DVDD should be tied to the analog and digital supply voltages,
respectively. The recommend voltages are defined in Table 3-5, and the maximum
voltages are given in Table 3-4. DVDD must be on whenever AVDD is on, so
DVDD should either be brought up first or at precisely the same time as AVDD.
AVDD can be turned off when not making a measurement to conserve power, since
all other operations are supported with DVDD. Under this condition, register values,
such as those in the Cycle Count Register, will be retained as long as DVDD is
powered. Also, AVDD must be within 0.1 V DVDD when AVDD is on.
AVSS and DVSS (Ground Pins)
AVSS and DVSS should be tied to the analog and digital ground, respectively.
Assuming the ground plane is clean, they may share a common ground. They may
have their own ground planes if this is more convenient from the standpoint of the
user’s circuit layout. DVSS and AVSS should be within 0.1 V of each other.