Spi timing requirements, Figure 4-4: spi timing diagram, 4 spi timing requirements – PNI RM3000 Sensor Suites User Manual

Page 27

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RM3000 & RM2000 Sensor Suite User Manual r08

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R

EXT

(External Timing Resistor)

R

EXT

ties to the external timing resistor for the high-speed clock. The recommended

value for the resistor and associated clock speed are defined in Table 3-1.

Sensor Drive and Measurement Pins

The various sensor drive and measurement pins should be connected to the

Geomagnetic Sensors. For a north-east-down (NED) reference frame, the

connections should be as defined in Figure 4-3.

4.4 SPI Timing Requirements

When implementing a SPI port, whether a dedicated hardware peripheral port or a software-

implemented port using general purpose I/O (also known as Bit-Banging), the timing

parameters (defined below in Figure 4-4 and specified in Table 4-2) must be met to ensure

reliable communication. Note that Standard Mode and Legacy Mode timing requirements

are identical with the exception of Legacy Mode utilizing the CLEAR line. The SPI clock

(SCLK) should run at 1 MHz or less. Generally data is considered valid while SCLK is

HIGH, and data is in transition when SCLK is LOW. The clock polarity used with the 3D

MagIC is zero (exclusively CPOL=0). Data is present on MISO or should be presented on

MOSI before the first low to high clock transition (exclusively CPHA = 0).

Figure 4-4: SPI Timing Diagram

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