AMD ATHLON K - Manual (Page 18)

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AMD Athlon™ Processor Model 4 Revision Guide 23614K—October 2003
Preliminary Information
24 Software Prefetches May Report A Page Fault
Products Affected. A4, A5, A6, A7, A9
Normal Specified Operation. Software prefetches should not report page faults if they encounter them.
Non-conformance. Software prefetch instructions are defined to ignore page faults. Under highly specific
and detailed internal circumstances, a prefetch instruction may report a page fault if both of the
following conditions are true:
■ The target address of the prefetch would cause a page fault if the address was accessed by an
actual memory load or store instruction under the current privilege mode;
■ The prefetch instruction is followed in execution-order by an actual or speculative byte-sized mem-
ory access of the same modify-intent to the same address.
PREFETCH and PREFETCHNTA/0/1/2 have the same modify-intent as a memory load access.
PREFETCHW has the same modify-intent as a memory store access.
The page fault exception error code bits for the faulting prefetch will be identical to that for a byte-
sized memory access of the same-modify intent to the same address.
Note that some misaligned accesses can be broken up by the processor into multiple accesses where at
least one of the accesses is a byte-sized access.
If the target address of the subsequent memory access of the same modify-intent is aligned and not
byte-sized, this errata does not occur and no workaround is needed.
Potential Effect on System. An unexpected page fault may occur infrequently on a prefetch instruction.
Suggested Workaround. Two workarounds are described for this erratum.
Kernel Workaround
The Operating System kernel can work around the erratum by allowing the page fault handler to
satisfy the page fault to an "accessible" page regardless of whether the fault was due to a load, store,
or prefetch operation. If the faulting instruction is permitted access to the page, return to it as usual.
(An "accessible" page is one for which memory accesses are allowed under the current privilege mode
once the page is resident in memory).
If the faulting instruction is trying to access an "inaccessible" page, scan the instruction stream bytes
at the faulting Instruction Pointer to determine if the instruction is a prefetch. (An "inaccessible"
page is one for which memory accesses are not allowed under the current privilege mode.) If the
faulting instruction is a prefetch instruction, simply return back to it; the internal hardware conditions
that caused the prefetch to fault should be removed and operation should continue normally. If it is not
a prefetch instruction, generate the appropriate memory access control violation as appropriate. The
performance impact of doing the scan is small because the actual errata is infrequent and does not
produce an excessive number of page faults that affect system performance.
General Workaround
If the page-fault handler for a kernel can be patched as described in the preceding kernel workaround,
no further action by software is required. The following general workarounds should only be
considered for kernels where the page-fault handler can not be patched and a prefetch instruction
could end up targeting an address in an "inaccessible" page.