AMD ATHLON K - Manual (Page 8)

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AMD Athlon™ Processor Model 4 Revision Guide 23614K—October 2003
Preliminary Information
11 PLL Overshoot on Wake-Up from Disconnect Causes Auto-Compensation Circuit to Fail
Products Affected. A4, A5, A6, A7, A9
Normal Specified Operation. The AMD Athlon processor model 4 PLL should return to the normal
operating frequency when reconnecting to the system bus after a disconnect where the PLL was
reduced to a lower operating frequency.
Non-conformance. The AMD Athlon processor model 4 PLL can exceed the normal operating frequency
when reconnecting to the system bus after a disconnect, causing a failure to maintain sufficient system
bus I/O drive strength levels in the driver compensation circuit. The compensation circuit attempts to
correct the drive strength, but if there is not sufficient time to perform this function, the system bus
cannot operate properly.
Potential Effect on System. The system hangs.
Suggested Workaround. The event can be avoided through BIOS manipulation of the reconnect timing
using the CLK_CTRL MSR. (See AMD Athlon™ and AMD Duron™ Processor CLK_CTRL MSR Settings,
order# 24478, for exact values.)
The time for the PLL to overshoot can be greatly shortened to reduce it to a very small time period that
does not enable the failure, and the time between the rampup and the reconnect to the system bus can
be increased such that a failure in the compensation circuit has enough time to recover before
reconnecting to the bus.
Resolution Status. Fix planned for a future revision.