AMD ATHLON K - Manual (Page 19)

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23614K—October 2003 AMD Athlon™ Processor Model 4 Revision Guide
Preliminary Information
Because the actual errata is infrequent, it does not produce an excessive number of page faults that
affect system performance. Therefore a page fault from a prefetch instruction for an address within an
"accessible" page does not require any general workaround.
Software can minimize the occurrence of the errata by issuing only one prefetch instruction per cache-
line (a naturally-aligned 64-byte quantity) and ensuring one of the following:
■ In many cases, if a particular target address of a prefetch is known to encounter this errata, simply
change the prefetch to target the next byte.
■ Avoid prefetching inaccessible memory locations, when possible.
■ In the general case, ensure that the address used by the prefetch is offset into the middle of an
aligned quadword near the end of the cache-line. For example, if the address desired to be
prefetched is "ADDR", use an offset of 0x33 to compute the address used by the actual prefetch
instruction as: "(ADDR & ~0x3f) + 0x33".
Resolution Status. No fix planned.