CH Tech Pulse Generator - Manual (Page 22)

16
4.2 PROGRAMMING SEQUENCE
The RUN bit in the Pulse Control Register is the basic On/Off control for pulse generation. A
separate output relay connects/disconnects the generated pulse to/from the BNC connector. The
output relay is controlled by the OEN bit in the PRI Register. Before enabling the RUN control
bit or output relay, be sure to program all of the timing and voltage level registers as prescribed in
this manual. Special care should be taken to check the registers for timing over runs and output
voltage levels. To prevent damage to the users circuitry, the following steps should be followed
when programming:
1) Disable the output relay and reset RUN.
2) Program Voltage References.
3) Setup Timing registers and control functions.
4) Enable the output relay.
5) Enable RUN.
4.3
NORMAL MODES OF OPERATION
The three normal modes of operation are single pulse, delayed pulse, and double pulse. All three
modes of operation and their relationship to trigger out are described below. The Trigger Output
signal indicates the beginning of a pulse cycle. It occurs 50-75ns after the RUN bit is set or the
trigger input signal goes high. The width of trigger out is equal to the pulse width range selected
(i.e., 25ns, 100ns, 1

s, etc.).
4.3.1 Single Pulse Mode
Single pulse mode produces the desired pulse immediately (approximately 25ns) after trigger out
and is selected when neither delayed or double pulse are selected.
4.3.2 Delayed Pulse Mode
When delayed pulse mode is selected, the pulse occurs the programmed delay time after the
trigger out (plus Approximately 25ns). To prevent a pulse overrun, ensure that the delay time and
the pulse width do not extend into the next cycle. The pulse generation logic takes about 75 nsec
to start; therefore, ensure that the delay time
+ the pulse width is less than the pulse repetition
interval

75 nsec.
4.3.3 Double Pulse Mode
The double pulse mode combines the functions of the single pulse mode and the delayed pulse
mode. The primary pulse occurs immediately after the trigger out and the secondary pulse occurs
the programmed delay time after trigger out. The width of both pulses are equal to the pulse
width clock range times the pulse width multiplier value. To prevent a pulse overrun, ensure that
the delay time and the pulse width do not extend into the next cycle. The pulse generation logic
takes about 75 nsec to start; therefore, ensure that the delay time
+ the pulse width is less than the
pulse repetition interval

75 nsec.