Kontron AT8902M - Manual (Page 46)

AT8902M Hardware Description
Page 3 - 13 AT8902M User Guide
CPLD
The CPLD is responsible for connecting the PPC to the IPMC and FUM and for handling the
serial interfaces of PPC, IPMC and FUM to the RS232 connector on the front panel. The host
interface between PowerPC and CPLD, realized by PPC’s External Bus Interface (EBC), is
used as CPLD-Register-Interface and as communication interface to IPM controller. The EBC
is configured as a demultiplexed 8 Bit Address/Data interface. For accesses to the IPMC Con-
troller, an EBC to LPC (Low Pin Count)-Bridge is included as protocol interface. The LPC inter-
face is for communication between IPMC and PPC over KCS protocol. An additional LPC-IF is
connected to the Fabric mezzanine.
The CPLD controls the LEDs for the whole board via shift registers. It handles the signals to
monitor the AMCs, fabric mezzanine module and the RTM and handles the signals for the line
drivers for the synchronization clocks and the AMC GbE support channels.
An internal multiplexer controls the serial interfaces from the PPC, the FUM and the IPMC. It
is possible to connect each device to the other or to the RS232 connector on the front panel.
3.1.6 Synchronization Clock
The Synchronization Clock Interface provides four differential pairs per AMC for clock distribu-
tion from the AMCs to the Hub Board and vice versa to enable applications that require the ex-
change of synchronous timing information among modules and consequently multiple boards
in a shelf. This allows modules to source clock(s) to the system in the case where it provides a
network interface function, or conversely to receive timing information from another carrier
board or module within the system. The four synchronization clock signals are TCLKA, TCLKB,
TCLKC and TCLKD, each supported by a differential pair. TCLKB and TCLKD are driven by
the AMCs to the backplane and TCLKA and TCLKC are driven from the backplane to the
AMCs. AMC1 and 2 cannot transmit or receive simultaneously signals to or from the backplane.
Either the CLK signals of AMC1 or the CLK signals of AMC2 are valid. The Hub Board cannot
receive any synchronization clocks from other carrier boards, it is only used for distribution. The
four differential clock signals are buffered by MLVDS differential line drivers that are controlled
by the IPMC and CPLD respectively.
For further details please refer AMC specification AMC0.RC1.1.
3.1.7 RTM Interface
The use of an RTM is optional. I/O signals from the Base Board are routed to Zone 3 where a
connector mates with the RTM. The RTM connection is compliant to the PICMG 3.0 standard.
For the connection between the Hub Board and the RTM two daughter card connectors with
40 differential pairs are used.
Each AMC Bay has eight (B1) or four (B2) pairs of generic interconnects to the RTM Zone 3
(AMC_B1_P13 to AMC_B1_P20 and AMC_B2_P17 to AMC_B2_P20). One SATA/FC inter-
face for mass storage from each AMC Slot is implemented (STOR0 and STOR1). Also an I2C
IPMI connection is implemented for an intelligent RTM.