Contemporary Research TD960801-0MC - Manual (Page 27)

TD960801-0MC
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3.2.5 EXTEND-A-BUS Engine
A high speed 32 Mhz 80C188 microprocessor provides the
computing power for the EXTEND-A-BUS. The ARCNET
port consists of a 20020 controller chip and coaxial bus or fiber
optic transceiver. The CAN port consists of a Intel 82527 CAN
controller and isolated 82C251 transceiver. The CAN port is
capable of generating interrupts at a high speed since the
EXTEND-A-BUS must listen to all CAN traffic. Back to back
CAN data frames can generate an interrupt every 94
µ
s at 500
kbps. The ARCNET buffers will also generate interrupts
making low latency interrupt handling a priority for the
EXTEND-A-BUS. Included in the engine is a 128Kx8 FLASH
ROM and 128Kx8 SRAM. An internal serial port is used to
update the firmware.
3.3 System Considerations
There are some design considerations when implementing a
remote bridging system.
By its very nature of storing and forwarding messages, the
EXTEND-A-BUS system introduces additional signal latency
which may disturb DeviceNet systems with tight timing
constraints. With the DeviceNet protocol, there has been little
evidence of any timing problems. However, the potential exists
for a system to erroneously signal a failed response to an action
when short cabling delays are assumed. On systems with very
fast DeviceNet scanners while operating at low data rates and
lightly load systems, the possibility exists for the master to issue
a comment to a slave and fail to wait for the slave’s response
before issuing another command assuming a failed response.
This is especially true for devices that support long fragmented
messages. The solution is to increase the interscan time to
either 5 to 10 ms in order to allow sufficient time for response.
Another solution is to increase the data rate on all devices to
500 kbps. Still another solution is to move problem devices to
the local segment (the same segment as the scanner) in order to
eliminate delays due to the EXTEND-A-BUSes.