Digital delay line, Block diagram, Pdr-04 – Pioneer PDR-04 User Manual
Page 91: Digital delay line block diagram
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PDR-04
Pin No.
Name
I/O
Function
81
TP4
0
For tests
82
TP5
1
83
XRFDET
1
RF detection signal input pin. H : No RF. L : RF
84
RECEN
1
Recording enable signal input pin. H ; Recordable. L : Not recordable
85
TP8
o
Test pin
86
DET4T
0
4T detection signal output pin
87
DET3T
0
3T detection signal output pin
88
EFM
0
EFM signal output pin
89
VDD
-
+5V power supply pin
90
VSS
-
Ground pin
91
ENCCK
0
Encode clock output pin
92
XEXTACK
0
ATIP synchronization notification signal output pin
93
XEXTSYNC
1
ATIP synchronization enable signal input pin
94
ATIPSYNC
1
ATIP sync signal Input pin
95
SUBSYNC
0
Subcode sync signal output pin
96
CCB
1
CPU interface method selection signal input pin. H : Sanyo CCB format. L: General serial format
97
CE
1
CPU interface chip enable signal input pin
98
CL
1
CPU interface data transfer clock input pin
99
Di
1
CPU interface data input pin
100
DO
0
CPU interface data output pin
ITK16124M (AUDIO DIGITAL BOARD ASSY: 10333,10334,10340)
DIGITAL DELAY LINE
Block Diagram
vcc
VOUT
91