Maxim Integrated MAXQ7666 - Manual (Page 118)

MAXQ7665/MAXQ7666 User’s Guide
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3.3.10 ADC Conversion Start Sources and Timing
The MAXQ7665/MAXQ7666 ADC supports three different conversion start sources: timers, ADC convert pin, and software writes. The
conversion start source provides the input trigger for the ADC to start acquisition and conversion. The ADC enable bit (ADCE) in the
analog power control register (APE) must be set so the ADC block is enabled for operation. If PGA > 1 is required, the PGA enable
(PGAE) bit and the PGA gain selection bits (PGG) must also be set. The ADC source select field (ADCS2:ADCS0) in the ADC control
register selects the ADC conversion start source, as shown in Table 3-8.
Table 3-8. ADC Conversion Start Source Selection
All three conversion start sources support single-edge or dual-edge modes of operation, which are determined by the ADCDUL bit.
When ADCDUL is set to 1, the ADC operates in dual-edge mode. The rising edge of the selected conversion start source causes the
ADC to power up and begin acquisition; the falling edge causes it to sample and perform a conversion. The ADC dual-edge mode is
valid only with PGA gain > 1. If ADCDUL is set to 1, make sure the PGA gain (selected by the PGG2:PGG0 bits in the APE register) is
greater than 1. The ADC dual-edge mode allows user control of the power-up and acquisition period. An ADC power-up delay is
required only if ADC is in auto shutdown from a prior conversion, otherwise, there is no ADC power-up delay. When ADCDUL is 0, the
ADC operates in single-edge mode. The rising edge of the selected conversion start source controls the entire conversion, i.e., power-
up, acquisition, and conversion. There is no restriction on the PGA gain selection when ADCDUL = 0. Table 3-9 summarizes ADC oper-
ation in dual- and single-edge modes.
ADC SOURCE SELECT
(ADCS2:ADCS0)
ADC CONVERSION START
SOURCE
DESCRIPTION
000 Timer 0
001 Timer 1
010 Timer 2
• Timer output is internally connected to ADC to act as the ADC conversion trigger
control.
• Configure timer for 8-bit or 16-bit PWM output operation.
011 Reserved, functions as 010 —
100 ADC Conversion Pin This configures the P0.4/ADCCNV pin as ADC conversion trigger control input pin.
101
ADC Conversion Pin with
Inverted Data
This configures the P0.4/ADCCNV pin as ADC conversion trigger control input pin.
ADCCNV pin input is inverted and used as ADC conversion trigger control.
110 Continuous Conversion
Writing 110 to ADCS triggers conversion. Once started, for PGA =1, ADC continuously
performs a conversion every 16 ADC clock cycles. For PGA > 1, ADC continuously
performs a conversion every 56 ADC clock cycles.
111 Start/Busy Bit Write to the start/busy bit triggers conversion.
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