Maxim Integrated MAXQ7666 User Manual
Page 166
MAXQ7665/MAXQ7666 User’s Guide
4-36
4.2.4.10 CAN 0 Transmit Message Acknowledgement Register (C0TMA)
Register Description:
CAN 0 Transmit Message Acknowledgement Register
Register Name:
C0TMA
Register Address:
Module 04h, Index 09h
Bit 15: Reserved. Read 0, write ignored.
Bits 14 to 0: Message Center 15 to 1 Transmit (C0TMA.15 to C0TMA.0). The C0TMA bits indicate which message center (1 to 15)
has been successfully transmitted. The contents of the C0TMA register are updated each time a new message is successfully trans-
mitted. The contents of the C0TMA0 register are automatically cleared following each read of C0TMA by the microcontroller. A bit value
of 1 indicates that the assigned message center has been successfully transmitted since the last read of the C0TMA register. A bit
value of 0 indicates no new message has been successfully transmitted since the last read of the C0TMA register. The corresponding
C0TMA bits are assigned to the following message centers. No interrupts are asserted because of the C0TMA settings. This register
works fully independent of the status bits in the CAN status register and the INTIN7:INTINT0 vector in the CAN interrupt register, and
independent of the INTRQ bit in the CAN message control registers.
Bit #
15
14
13
12
11
10
9
8
Name
—
C0TMA.15 C0TMA.14 C0TMA.13 C0TMA.12 C0TMA.11 C0TMA.10 C0TMA.9
Reset
0 0 0 0 0 0 0 0
Access
r
r
r
r
r
r
r
r
Bit #
7
6
5
4
3
2
1
0
Name C0TMA.8
C0TMA.7
C0TMA.6
C0TMA.5
C0TMA.4
C0TMA.3
C0TMA.2
C0TMA.1
Reset
0 0 0 0 0 0 0 0
Access
r
r
r
r
r
r
r
r
r = read
Note: This register is cleared to 0000h on all forms of reset, including the reset established by the CRST bit.
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