Maxim Integrated MAXQ7666 - Manual (Page 254)

MAXQ7665/MAXQ7666 User’s Guide
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7.3.1 16-Bit Timer: Auto-Reload/Compare
The 16-bit auto-reload/compare mode for the Type 2 timer is in effect when the timer-mode select bit (T2MD) is cleared and the cap-
ture/compare function definition bits are both cleared (CCF1:CCF0 = 00b). The timer value is contained in the T2Vx register. The timer
run control bit (TR2) starts and stops the 16-bit timer. The input clock for the 16-bit Type 2 timer is defined as the system clock divid-
ed by the ratio specified by the T2DIV2:T2DIV0 prescale bits. The timer begins counting from the value contained in the T2Vx register
until an overflow occurs. When an overflow occurs, the reload value is reloaded instead of the x0000h state. The timer overflow flag
(TF2) is set every time that an overflow condition (T2Vx = 0xFFFFh) is detected. If the Type 2 timer interrupts have been enabled (ET2
= 1), the TF2 flag can generate an interrupt request. When operating in compare mode, the capture/compare register, T2Cx, is com-
pared versus the timer value registers. Whenever a compare match occurs, the capture/compare status flag (TCC2) is set. If the Type
2 timer interrupts have been enabled (ET2 = 1), this event can generate an interrupt request. If the capture/compare register is set to
a value outside of the timer counting range, a compare match is not signaled and the TCC2 flag is not set. Internally, a timer output
clock is generated that toggles on the cycle following any compare match or overflow, unless the compare match value has been set
equal to the overflow condition, in which case, only one toggle occurs. This clock, if enabled by the T2OE0 bit, can be output on the
timer pin Tx. Note: For an interrupt to occur, the global enable bits IM2 (for timer 0 and timer 1) and IM3 (for timer 2) in the IMR periph-
eral register and IGE in the IC peripheral register must also be enabled.
• Output Enable (PWM Out). The output enable bit (T2OE0) enables the timer output clock to be presented on the timer
input/output pin Tx (0 for timer 0, 1 for timer 1). Note: T2 is not supported on the 48- and 56-pin packages. Thus, timer 2 can
serve only as an internal timer.
• Polarity Control. The polarity control bit (T2POL0) can be used to modify (invert) the enabled clock output to the pin. The
enabled clock output toggles on each compare match or overflow. The T2POL0 bit is logically XORed with the timer output sig-
nal, therefore setting T2POL0 will result in a high starting state. The T2POL0 bit can be changed any time, however, the assigned
T2POL0 state will take effect on the external pin only when the corresponding T2OE0 bit is changed from 0 to 1. When gener-
ating PWM output, note that changing the compare match register can result in a perceived duty cycle inversion if a compare
match is missed or multiple compare matches occur during the reload to overflow counting.
• Gated. To use the Tx pin as a timer input clock gate, the T2OE0 bit must be cleared to 0 and the G2EN bit must be set to 1.
When T2OE0 = 1, the G2EN bit setting has no effect. When T2OE0 is cleared to 0, the respective polarity control bit is used to
modify the polarity of the input signal to the timer. In the gated mode, the timer input clock is gated anytime the external signal
matches the state of the T2POL0 bit. This means that the default clock gating condition for the Tx pin is logic-low (since T2POL0
= 0 default). Setting T2POL0 = 1 results in the timer input clock being gated when the Tx pin is high.
• Single-Shot. When operating in 16-bit compare mode, the single-shot is used to automate the generation of single pulses under
software control or in response to an external signal (single-shot gated). To generate single-shot output pulses solely under soft-
ware control, the G2EN bit should be cleared to 0, the output enables and polarity controls should be configured as desired,
and the single-shot bit should be set to 1. Writing the single-shot bit effectively overrides the TR2 = 0 condition until timer over-
flow/reload occurs. The single-shot bit is automatically cleared once the overflow/reload occurs.
Writing SS2 and TR2 = 1 at the same time still causes the SS2 bit to stay in effect until an overflow/reload occurs, however, since
TR2 was also written to a 1, the specified PWM output continues even after SS2 becomes clear.
• Capture/Reload Control. For the 16-bit compare operating mode, the CPRL2 bit is not used.
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