11 adc interrupts -32, 12 using the adc -33, 12 using the adc – Maxim Integrated MAXQ7666 User Manual

Page 123

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MAXQ7665/MAXQ7666 User’s Guide

3-33

3.3.12 Using the ADC

The flow chart in Figure 3-13 highlights all the steps required for initializing and using the ADC.

Figure 3-13. Flow Chart for Initializing and Using the ADC

SELECT IN ADC CONTROL REGISTER
ACNT:
A) DIFFERENTIAL CONVERSION.
B) SELECT UNIPOLAR OR BIPOLAR MODE.
C) SET ADCASD IF ADC AUTO
SHUTDOWN IS REQUIRED.

SELECT IN ACNT REGISTER (CONT’d.):
D) ADC CONVERSION START SOURCE:
TIMERS 0–2, ADCCONV PIN, SW WRITE.
E) SINGLE OR DUAL EDGE: FOR ADC
LOGIC-CONTROLLED ACQUISITION
TIME, SELECT SINGLE EDGE (0); FOR
USER-CONTROLLER ACQUISITION
TIME, SELECT DUAL EDGE (1) MODE
(PGA GAIN > 1).
F) ADC INPUT CHANNEL.

START ADC CONVERSION:
DEPENDING ON ADC CONVERSION
START SOURCE SET TIMER ENABLE
(PIN IS ALREADY I/P FROM BELOW,
LEFT) OR ADC START/BUSY BIT IN
ACNT TO TRIGGER CONVERSION.
NOTE: FOR CONTINUOUS MODE,
SELECTING 110 IN ADCS FIELD
TRIGGERS CONVERSION.

IF POLLED CONVERSION, WAIT FOR
ADCRY BIT IN ADC STATUS REGISTER
TO BE SET BEFORE READING THE ADC
DATA REGISTER. OTHERWISE, READ
ADC DATA AFTER ADC DATA READY
INTERRUPT.

READ AND SAVE 12-BIT ADC RESULT
(CODE

12

) FROM ADC DATA REGISTER.

THE DIFFERENTIAL ANALOG INPUT
VOLTAGE AS A FUNCTION OF REFADC,
PGA GAIN FACTOR (PGA_GF), AND THE
DIGITAL OUTPUT CODE (CODE
DETERMINED WITH THE EQUATION
GIVEN IN SECTION 3.3.5.

SELECT ADC CLOCK DIVIDE RATIO IN THE
OSCC REGISTER.

ENABLE ADC: SET ADCE IN ANALOG
POWER ENABLE REGISTER. ENABLE PGA,
IF REQUIRED, AND SET PGG FOR GAIN > 1.
IF PGA IS ENABLED, GIVE 5

μs POWER-

UP/WARMUP TIME BEFORE CONVERSION.

IF CONVERSION START SOURCE IS
GOING TO BE ONE OF THE TIMERS,
CONFIGURE TIMER IN 16-BIT PWM OR 8-
BIT PWM OUTPUT MODE. NOTE: TIMER
OUTPUT IS INTERNALLY SELECTED AS
THE ADC START TRIGGER CONTROL.

IF CONVERSION START SOURCE IS FROM
EXTERNAL ADCCONV PIN, ENSURE PIN IS
CONFIGURED AS INPUT.

TO GET ADC DATA READY INTERRUPT
AFTER A CONVERSION, SET ADCIE BIT IN
ANALOG INTERRUPT ENABLE REGISTER.
ALSO, ENABLE GLOBAL INTERRUPT
CONTROL BITS IM5 IN IMR AND IGE IN IC
PERIPHERAL REGISTER.

Maxim Integrated

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