Clevo M860TU - Manual (Page 95)

Schematic Diagrams
Board to Board CON/TPM B - 39
B.Schematic Diagrams
Board to Board CON/TPM
U S B _P P 8 14
W E B 1 # 2 2
S P K O U T L + 2 6
3 . 3 V
R 6 9 3 *3 3 _ 04
Z 3 80 9
T P M_ B A D D
3 . 3 V 2 , 1 4 , 1 5, 1 6 , 1 9 , 2 1, 2 7 , 2 8 , 2 9, 3 0 , 3 1 , 3 2, 3 4 , 3 6 , 3 7
I N T _ S E R I R Q 1 5 , 22 T P _ C LK
5 V 1 5 , 1 6 , 1 7, 2 1 , 3 0 , 3 1, 3 2 , 3 4 , 3 5
S P K O U T R - 2 6
V D D 3 2, 1 3 , 1 9 , 2 2, 2 4 , 2 9 , 3 2, 3 3 , 3 4 , 3 7
C 77 4
* 1u _ 1 0V _0 6
R 6 9 5 1 0K _0 4
C 7 6
*1 8 0 P _ 0 4
C 5 2
. 1u _ 1 6V _0 4
C 7 76 *1 2 p _N P O _0 4
R 6 9 6 *1 0 K _ 0 4
S P K O U T R + 26
3 . 3 V S 2, 3, 5 , 9 , 1 2 , 1 3, 1 4 , 1 5 , 1 6, 1 9 , 2 0 , 2 1, 2 2 , 2 3 , 2 4, 2 5 , 2 6 , 2 8, 3 0 , 3 2 , 3 3, 3 5 , 3 6 , 3 7
M _ B T N # 3 3
T P M _ B A D D
C 7 7 7 * 12 p _ N P O_ 0 4
C 5 1
. 1 u _ 16 V _ 0 4
5 V T P
R 1 0 6 *1 0 mi l _ s ho rt
P Q6 6
2 N 7 00 2
G
D S
C 5 3
. 1 u _ 16 V _ 0 4
C 7 7 8 *1 0 p_ N P O_ 0 4
3 . 3 V S
L P C _A D 1 1 3 , 2 2
S U S B # 1 5, 2 1 , 2 2
R 12 4 *1 0 m i l_ s h o rt
R 1 1 7
1 0K _0 4
PVT: ADD TPM Circuit For EPSON
P J 1 9
2 0m i l
1 2
HI : ACCESS LOW : NORMAL ( Inte rnal PD )
L P C _A D 2 1 3 , 2 2 C 7 72
* 0 . 1u _ 1 6 V _ 04
R 3 9 3
3 30 K _ 0 4
T P M_ P P
Q2 4
A O 34 0 9
G
D S
T P _ D A TA 2 2
Z 3 8 04
S U S B #
5 V S
W E B 0 #
Z 3 8 05
C 1 82
*4 7 p _5 0 V _ 0 4
HOT KEY (M/B side)
TPM_PP
6-03-09635-0H1
S U S B L 30 , 3 3
Q5 2 2 N 7 0 0 2W
G
D
S
X8
* 3 2. 7 6 8 K H z
1
4 3
2
P L T _R S T # 5 , 1 4, 22 , 3 7
R 37 8 *1 0 m i l_ s h o rt
5 V S 1 3, 1 6 , 1 7 , 2 1, 2 3 , 2 5 , 2 6, 2 8 , 3 3 , 3 7
C 54
*. 1 u _ 1 6V _0 4
R 3 94
1 M _0 4
C 7 7
* 1 80 P _ 0 4
P C 2 38
0 . 1 u _5 0 V _ 0 6
asserted before entering S3
5 V
T P _ D A T A
P C L K _ T P M
A P _K E Y # 2 2
TPM
U 34
* S LB 96 3 5 T T
1 7
2 6 2 3
2 0 10
13
24 19
2 2
2 1
1 6
2 7
1 5
4
11
18
25
6 2
14
8
9
7
1 3 1 2
2 8
5
L A D 3
L A D 0 L A D 1
L A D 2 V D D 1
XT A L I
V D D 3
V D D 2
L F R A M E #
L C L K
L R E S E T#
S E R I R Q
C L K R U N #
G N D _ 1
G N D _ 2
G N D _ 3
G N D _ 4
G P I O G P I O 2
X T A L O
T E S T I
T E S T B I / B A D D
P P
N C _ 1 N C _ 2
N C _ 3
L P C P D #
V S B
L P C _A D 0 1 3 , 2 2
L P C _A D 3 1 3 , 2 2
Z 2 2 21
T P _ C LK 2 2
T P M _ XI
W E B 2 # 2 2
C 77 3
*0 . 1 u _ 16 V _ 0 4
C 1 3 8
1 0 u_ 1 0 V _ 0 8
R 1 0 7 *0 _ 0 6
LPC reset timing:
3 . 3 V S
85201-12
C 7 8 * 1 8 0P _ 0 4
JL E D 2
B C O N 1 2
1 2
3
4
5
6
7
8
9
1 0
1 1
1 2
C 1 8 5
. 1 u_ 1 6 V _ 0 4
R 12 3 *1 0 m i l_ s h o rt
TPM 1.2
C 18 4
. 1 u _1 6 V _ 0 4
C 1 8 0
1 u _ 6. 3V _ 0 4
LP C _ F R A ME # 1 3 , 2 2
V I N
P M _ C L K R U N # 1 5, 2 2
3 . 3 V S
5 V S
HI : 4E/4F h
LOW : 2E / 2 F h
S P K O U T L - 2 6
P Q 67
2 N 7 0 0 2
G
D S
T P M _ XO
R 1 16
1 0 K _ 0 4
P R 2 2 4
1 00 K _ 0 4
C 48 6 1 u _6 . 3 V _ 0 4
C 1 8 3
* 4 7p _ 5 0V _0 4
V I N 2 8 , 2 9 , 3 0, 3 1 , 3 2 , 3 3, 3 4 , 3 5 , 3 7
P C L K _T P M 1 8
W E B 0#
CLICK(M/B side)
T P M _ P P
R 6 9 4 *1 0 K _ 0 4
C 7 75
* 0. 1u _ 1 6 V _0 4
3 . 3 V S
Z 3 8 0 8
C 5 5
* . 1 u_ 1 6 V _ 0 4
J T P 1
G C O N 1
1
2
3
4
6
8
9
1 0
5
7
1
2
3
4
6
8 9
1 0
5
7
C 7 7 1
*0 . 1 u _1 6 V _ 0 4
LPCPD# inactive to LRST# inactive 32~96us
U S B _P N 8 14
K B C _ L P C P D # 1 5
5V TP
C 50
. 1 u _1 6 V _ 0 4
D D ON # 3 3
R 69 7 * 10 0 _ 0 4
C 7 5 * 18 0 P _ 0 4
TPM_BADD
Z 3 80 7
5 V _T P
T P M_ T E S T
Sheet 38 of 42
Board to Board
CON/TPM