ADLINK PCI-9846 - Manual (Page 47)

Operation Theory 37
Figure 3-9: Analog Trigger Conditions
3.4.4 PXI STAR Trigger
When you select PXI STAR as the trigger source, the PXI-9816/
PXI-9826/PXI-9846 can accept a TTL-compatible digital signal as
a trigger signal. The trigger occurs when a rising edge or falling
edge is detected at PXI STAR. You can use software to configure
the trigger polarity. The minimum pulse width requirement of this
digital trigger signal is 20 ns.
3.4.5 PXI Trigger Bus
The PXI-9816/PXI-9826/PXI-9846 utilizes PXI Trigger Bus[0..7] as
System Synchronization Interface (SSI). Using the interconnected
bus provided by PXI Trigger Bus, you can easily synchronize mul-
tiple modules.
When configured as input, the PXI-9816/PXI-9826/PXI-9846 is
served as a slave module and can accept three different SSI sig-
nals, SSI_TRG1, SSI_TRG2 and SSI_START_OP. When config-
ured as output, the PXI-9816/PXI-9826/PXI-9846 is served as a
master module and can output SSI_TRG1, SSI_TRG2 or
SSI_START_OP to PXI Trigger Bus. Each signal can be routed
from one of the PXI Trigger Bus[0..7] by software programming.
For more detail about these signals, please refer to Section “3.7”
on page 44.
Trigger Level
Positive-Slope Trigger Event
Occurs
Negative-Slope Trigger
Event Occurs
Analog
Signal