ADLINK PCI-9846 - Manual (Page 57)

Operation Theory 47
3.7.1 SSI_TIMEBASE
As an output, the SSI_TIMEBASE signal outputs the onboard
LVTTL timebase through PXI trigger bus.
As an input, the PCI/PXI-9816/26/46 accepts the SSI_TIMEBASE
signal to be the source of timebase.
Signal Name Direction Description Location
SSI_TIMEBASE Input/Output
Timebase signal through
SSI
pin 1
SSI_TRIG1 Input/Output
Trigger signal through
SSI
pin 11
SSI_TRIG2 Input/Output
Clocked trigger signal
through SSI
pin 9
SSI_START_OP Input/Output
Acquisition start signal
in pre-trigger or middle-
trigger mode
pin 7
GND - Ground
pins 2, 4, 6, 8,
10, 12, 14, 16,
18, 20
NC - No Connection pins 3, 13
Reserved Input/Output Reserved for future use pins 5, 15, 17, 19
Table 3-5: SSI Signal Locations and Pin Definition