Altera 8B10B Encoder/Decoder MegaCore Function - Manual (Page 17)

Chapter 2: Getting Started 2–7
Compile the Design
May 2011 Altera Corporation 8B10B Encoder/Decoder MegaCore Function User Guide
1 In all cases, the testbench is in Verilog HDL, therefore a license to run mixed language
simulations is required to run the testbench with the VHDL model.
Altera recommends that you disable the auto-ROM replacement feature in the
Quartus II software. Enabling this feature produces a smaller but slower MegaCore
function.
Compile the Design
You can use the Quartus II software to compile your design. Refer to Quartus II Help
for instructions on compiling your design.
Program a Device
After you have compiled your design, program your targeted Altera device, and
verify your design in hardware.