Altera Cyclone V GX FPGA - Manual (Page 28)

6–12 Chapter 6: Board Test System
The Clock Control
Cyclone V GX FPGA Development Kit October 2012 Altera Corporation
User Guide
The Clock Control
The Clock Control application sets the Si571 programmable oscillator to any
frequency between 10 MHz and 810 MHz with eight digits of precision to the right of
the decimal point.
The Si5338 device has four independently programmable outputs. All four outputs
are programmable between 16 KHz and 350 MHz. All four outputs can support the
higher frequencies, but they cannot be programmed for multiple frequencies above
350 MHz. If you want multiple outputs above 350 MHz, all outputs above 350 MHz
must be the same frequency, and must be frequencies from 367 MHz to 473.33 MHz or
from 550 MHz to 710 MHz. Channel 0 of Si5338 drives a 2-to-4 buffer that drives a
copy of the clock to all four edges of the FPGA.
The Clock Control application runs as a stand-alone application. ClockControl.exe
resides in the <install
dir>\kits\cycloneVGX_5cgxfc7df31_fpga\examples\board_test_system directory.
On Windows, click Start > All Programs > Altera > Cyclone V GX FPGA
Development Kit
<version> > Clock Control to start the application.
f For more information about the Si571/Si5388 and the Cyclone V GX FPGA
development board’s clocking circuitry and clock input pins, refer to the Cyclone V GX
FPGA Development Board Reference Manual .
The Clock Control communicates with the MAX V device on the board through the
JTAG bus. The Si571 programmable oscillator is connected to the MAX V device
through a 2-wire serial bus.
Figure 6–6 shows the Clock Control U25 tab.
Figure 6–6. The Clock Control - U25 Tab