Altera Device-Specific Power Delivery Network - Manual (Page 15)

Chapter 1: User Guide for the Device-Specific Power Delivery Network (PDN) Tool 1–11
Major Tabs of the PDN Tool
September 2012 Altera Corporation Device-Specific Power Delivery Network (PDN) Tool User Guide
Two-Terminal Decoupling Capacitors
The decoupling capacitors section contains the default ESR and ESL values for the
various two-terminal capacitors in different footprints (0201, 0402, 0603, 0805, and
1206). You also have the option of either modifying the default values or entering
your own commonly used custom values in the Custom field. If you are using a
capacitor with a footprint that is not available in the tool, you must use the Custom
field to enter the capacitor parasitics and the corresponding mounting inductance.
The decoupling capacitors section also provides the option for the user defined
capacitors (such as User1,...,User4). You can define the ESR and ESL parasitics for the
various footprints and enter the corresponding capacitor value in the Decap Selection
tab. Choose the corresponding footprint when defining the capacitor values.
Bulk Capacitors
The bulk capacitors section contains the commonly used capacitor values for
decoupling the power supply at mid/low frequencies. You can change the default
values to reflect the parameters specific to the design.
X2Y Decoupling Capacitors
The X2Y decoupling capacitors section contains the default ESR and ESL values for
the various X2Y capacitors in different footprints (0603, 0805, 1206, and 1210). You
also can replace the default ESR and ESL values with your own commonly used
custom values.
BGA Via and Plane Capacitance
The BGA via and plane capacitance section provides an option to directly enter the
values for effective via loop inductance under the BGA and plane capacitance during
the pre-layout phase when no design-specific information is available.
If you have access to design-specific information, you can ignore this section and
enter the design-specific information in the Plane Cap and BGA Via tabs that
calculate the plane capacitance and the BGA via parasitics, respectively.
VRM Library
The VRM section lists the default values for both the linear and switcher regulators.
You can change the VRM parasitics listed under the linear/switcher rows or add the
custom parasitics for the VRM relevant to the design in the Custom field.
Spreading R, L Parasitics
The spreading R, L library provides various options for the default effective spreading
inductance values that the decoupling capacitors see with respect to the FPGA based
on the quality of the PDN design. You can choose a Low value of effective spreading
inductance if you have optimally designed your PDN Network. Optimum PDN
design involves implementing the following design rules:
■ PCB stackup that provides a wide solid power/ground sandwich for a given
supply with a thin dielectric between the planes. This minimizes the current loop,
which reduces the spreading inductance. The thickness of the dielectric material
between the power/ground pair directly influences the amount of spreading/loop
inductance that a decoupling cap can see with respect to the FPGA.