Altera Transceiver Signal Integrity Development Kit, Stratix V GX Edition - Manual (Page 14)

2–6 Chapter 2: Board Components
Featured Device: Stratix V GX
Transceiver Signal Integrity Development Kit July 2012 Altera Corporation
Stratix V GX Edition Reference Manual
Featured Device: Stratix V GX
The Stratix V GX development board features the Stratix V GX 5SGXEA7N2F40C2N
device (U29) in a 1517-pin FineLine BGA package.
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For more information about the Stratix V device family, refer to the Stratix V Device
Handbook .
Table 2–2 describes the features of the Stratix V GX 5SGXEA7N2F40C2N device.
Table 2–3 lists the Stratix V GX component reference and manufacturing information.
I/O Resources
Table 2–4 summarizes the FPGA I/O usage by function on the Stratix V GX
transceiver signal integrity development board.
Table 2–2. Stratix V GX 5SGXEA7N2F40C2N Features
ALMs
Equivalent
LEs
Registers
M20K
Blocks
MLAB
Blocks (Mb)
18-bit × 18-bit
Multipliers
PLLs
Transceiver
Channels
(12.5 Gbps)
Package Type
358,500 622,000 939,000 2,560 7.16 512 28 36
1517-pin
FineLine BGA
Table 2–3. Stratix V GX Component Reference and Manufacturing Information
Board
Reference
Description Manufacturer
Manufacturing
Part Number
Manufacturer
Website
U29
FPGA, Stratix V GX F1517, 622K
LEs, lead-free
Altera Corporation 5SGXEA7N2F40C2N www.altera.com
Table 2–4. Stratix V GX I/O Usage Summary (Part 1 of 3)
Function I/O Type I/O Count Description
FPGA Transceiver Clocks
Programmable differential clock LVDS input 4 Differential REFCLK input to feed the even-
numbered channels on the left side of the Stratix V
GX device.
Programmable differential clock LVDS input 4 Differential REFCLK input to feed the odd-numbered
channels on the left side of the Stratix V GX device.
Programmable differential clock LVDS input 4 Differential REFCLK input to feed the even-
numbered channels on the right side of the Stratix V
GX device.
Programmable differential clock LVDS input 4 Differential REFCLK input to feed the odd-numbered
channels on the right side of the Stratix V GX
device.
External differential clock inputs LVDS input 4 pairs Differential REFCLK input for one SMA pair per
clock buffer.
FPGA Global Clocks
50-MHz clock 2.5-V CMOS input 1 Global clock input.