Altera Arria V GT FPGA Development Board - Manual (Page 70)

2–60 Chapter 2: Board Components
Memory
Arria V GT FPGA Development Board December 2014 Altera Corporation
Reference Manual
T3 DDR3B_A13 P31 1.5-V SSTL Class I Address bus
M2 DDR3B_BA0 M32 1.5-V SSTL Class I Bank address bus
N8 DDR3B_BA1 N32 1.5-V SSTL Class I Bank address bus
M3 DDR3B_BA2 J34 1.5-V SSTL Class I Bank address bus
K3 DDR3B_CASN L33 1.5-V SSTL Class I Row address select
K9 DDR3B_CKE E31 1.5-V SSTL Class I Column address select
K7 DDR3B_CLK_N C30 1.5-V SSTL Class I Differential output clock
J7 DDR3B_CLK_P B30 1.5-V SSTL Class I Differential output clock
L2 DDR3B_CSN L34 1.5-V SSTL Class I Chip select
K1 DDR3B_ODT L31 1.5-V SSTL Class I On-die termination enable
J3 DDR3B_RASN K34 1.5-V SSTL Class I Row address select
T2 DDR3B_RESETN G30 1.5-V SSTL Class I Reset
L3 DDR3B_WEN M33 1.5-V SSTL Class I Write enable
L8 DDR3B_ZQ2 — 1.5-V SSTL Class I ZQ impedance calibration
DDR3B (U6)
E7 DDR3B_DM0 J30 1.5-V SSTL Class I Write mask byte lane
D3 DDR3B_DM1 J29 1.5-V SSTL Class I Write mask byte lane
E3 DDR3B_DQ0 B28 1.5-V SSTL Class I Data bus byte lane
F7 DDR3B_DQ1 C29 1.5-V SSTL Class I Data bus byte lane
F2 DDR3B_DQ2 R30 1.5-V SSTL Class I Data bus byte lane
F8 DDR3B_DQ3 A29 1.5-V SSTL Class I Data bus byte lane
H3 DDR3B_DQ4 A28 1.5-V SSTL Class I Data bus byte lane
H8 DDR3B_DQ5 L30 1.5-V SSTL Class I Data bus byte lane
G2 DDR3B_DQ6 D30 1.5-V SSTL Class I Data bus byte lane
H7 DDR3B_DQ7 D29 1.5-V SSTL Class I Data bus byte lane
D7 DDR3B_DQ8 L28 1.5-V SSTL Class I Data bus byte lane
C3 DDR3B_DQ9 M28 1.5-V SSTL Class I Data bus byte lane
C8 DDR3B_DQ10 H28 1.5-V SSTL Class I Data bus byte lane
C2 DDR3B_DQ11 C28 1.5-V SSTL Class I Data bus byte lane
A7 DDR3B_DQ12 D28 1.5-V SSTL Class I Data bus byte lane
A2 DDR3B_DQ13 F28 1.5-V SSTL Class I Data bus byte lane
B8 DDR3B_DQ14 M29 1.5-V SSTL Class I Data bus byte lane
A3 DDR3B_DQ15 N29 1.5-V SSTL Class I Data bus byte lane
G3 DDR3B_DQS_N0 P30 1.5-V SSTL Class I Data strobe N byte lane
B7 DDR3B_DQS_N1 T29 1.5-V SSTL Class I Data strobe N byte lane
F3 DDR3B_DQS_P0 N30 1.5-V SSTL Class I Data strobe P byte lane
C7 DDR3B_DQS_P1 R29 1.5-V SSTL Class I Data strobe P byte lane
DDR3B (U12)
E7 DDR3B_DM2 J30 1.5-V SSTL Class I Write mask byte lane
Table 2–32. DDR3 x32 Devices Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 3)
Board Reference
Schematic
Signal Name
Arria V GT FPGA
Pin Number
I/O Standard Description