Zilog EZ80F916 - Manual (Page 244)

UM014423-0607
ZiLOG Developer Studio II
eZ80Acclaim! ® User Manual
224
ADDRESSING MODES
This section discusses the addressing modes supported by the eZ80Acclaim! Macro
Assembler.
Table 11. eZ80Acclaim! Addressing Modes
Addressing Modes Symbolic Name Notes
8-Bit Register Mode A
B
C
D
E
H
L
16/24-Bit Register Mode BC
DE
HL
IX
IY
Indirect Register Mode (BC)
(DE)
(HL)
(IX)
(IY)
Indirect Register Mode Plus Offset (IX+dd) dd must be in the range of –128<dd<127.
(IY+dd) dd must be in the range of –128<dd<127.
16/24-Bit Direct Addressing Mode xxxxH or xxxxxxH For 24-bit values, ADL must equal 1.
PC Relative Addressing Mode PC
Single-Bit Flags ADL Not directly accessible but can be changed by suffixed
JP and CALL instructions.
IEF1
IEF2
MADL