Ld r, (ix/y+d), Operation, Description – Zilog EZ80F916 User Manual
Page 233: Condition bits affected, Attributes
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eZ80
®
CPU
User Manual
UM007715-0415
CPU Instruction Set
224
LD r, (IX/Y+d)
Load Register
Operation
r
(IX/Y+d)
Description
The r operand is any of the 8-bit CPU registers A, B, C, D, E, H, or L. The (IX/Y+d) oper-
and is an 8-bit value at the memory location specified by the contents of the Index Regis-
ter, IX or IY, added to the two’s-complement displacement d. This 8-bit value is written to
the specified r register.
Condition Bits Affected
None.
Attributes
jj
identifies the A, B, C, D, E, H, or L register and is assembled into one of the opcodes
.
Mnemonic Operand
ADL Mode Cycle
Opcode (hex)
LD
r
,(IX+d)
X
4
DD, jj, dd
LD.S
r
,(IX+d)
1
5
52, DD, jj, dd
LD.L
r
,(IX+d)
0
5
49, DD, jj, dd
LD
r
,(IY+d)
X
4
FD, jj, dd
LD.S
r
,(IY+d)
1
5
52, FD, jj, dd
LD.L
r
,(IY+d)
0
5
49, FD, jj, dd
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