Zilog Z16C30 - Manual (Page 109)

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Z16C30 USC ®
U SER ' S M ANUAL
UM97USC0100
Z ILOG
5.20 COMMANDS (Continued)
Enter Hunt Mode (RCmd:=0011): this command forces
the Receiver into “Hunt Mode” immediately, regardless of
its previous state. In synchronous modes, this means that
the Receiver starts searching for a Sync or Flag sequence.
In asynchronous modes it starts searching for a start bit. In
any mode, the Receiver discards any partial character that
was in progress when software issued the command.
Load RCC and/or TCC (RTCmd:=01101-01111): these
commands load the Receive and/or Transmit Character
Counter from the Receive and/or Transmit Count Limit
Register (RCC from RCLR and/or TCC from TCLR). This
may enable or disable character counting. If software has
enabled the Transmit Control Block feature in the TxCtrlBlk
field of the Channel Control Register (CCR15-14=01 or
10), a Load TCC or Load RCC and TCC command also
conditions the Transmitter to treat the next data written to
the Transmit Data Register as a TCB.
Load TC0 and/or TC1 (RTCmd:=10001-10011): these
commands load the counter in Baud Rate Generator 0
and/or 1 from the Time Constant 0 and/or 1 Register (BRG0
from TC0R and/or BRG1 from TC1R). If software has
programmed a BRG for single cycle mode (HCR1=1 for
BRG0 or HCR5=1 for BRG1) and it has stopped after
counting down to zero, loading a BRG via one of these
commands also enables it to count. See Chapter 4 for more
information about the BRG’s.
Purge Rx (RTCmd:=11001): on USCs manufactured after
June 1993, this command purges (clears, empties) both
the main RxFIFO and the RCC FIFO described in an earlier
section. It combines the functions of the ClearRCCF bit in
the Channel Command/Status Register (CCSR13) and the
Purge RxFIFO command described in the next paragraph,
including the latter command’s function of reloading the
RCC. This command is intended to be used after an Enter
Hunt mode command in handling an Rx Overrun condition,
and ensures that the two FIFOs are synchronized with
respect to End-of-Frame conditions.
Software can use the device identification features de-
scribed in “Determining the Device Revision Level” in
Chapter 8, to determine whether it can issue this com-
mand, or whether it has to issue the two separate com-
mands noted above.
Purge Rx and/or Tx FIFO (RTCmd:=01001-01011): these
commands remove all entries from the RxFIFO and/or
TxFIFO. They also reload the Receive and/or Transmit
Character Counter from the Receive and/or Transmit Count
Limit Register (RCC from RCLR and/or TCC from TCLR).
This may enable or disable character counting. If software
has enabled the Transmit Control Block feature in the
TxCtrlBlk field of the Channel Control Register (CCR15-
14=01 or 10), a Purge Tx FIFO command also conditions
the Transmitter to treat the next data written to the Transmit
Data Register as a TCB. If software is using an external
Transmit DMA channel, a Purge Tx FIFO command may
cause the /TxREQ pin to be asserted immediately, while if
it’s using Transmit Data interrupts, the command may
cause the /INTA or /INTB pin to be asserted immediately.
(The previous two sentences also apply to a Purge Rx and
Tx FIFO command.)
On USCs manufactured before June 1993, the Purge
RxFIFO and Purge Rx and TxFIFO commands did not clear
a hidden “holding register” located between the Rx shift
register and the RxFIFO. This caused problems if a very
fast processor responded to an HDLC Abort interrupt and
performed a Purge RxFIFO command before the final
character before the Abort was transferred from the hold-
ing register to the RxFIFO. In this case, this character
would then go into the RxFIFO and finally emerge as an
extraneous 1-character “frame.” USCs manufactured after
June 1993 deal with this problem in two separate ways: 1)
they don’t set the Break/Abort flag until after the character
before the Abort is in the RxFIFO, and 2) they clear the
holding register as a result of either Purge RxFIFO com-
mand or a Purge Rx command. Thus, they will never
produce such a 1-character frame, regardless of how fast
the processor is.
Reset Highest IUS (RTCmd:=00010): Chapter 7 describes
how this command clears the highest-priority Interrupt
Under Service latch in the channel that’s currently set (if
any).
Select D15-8 or D7-0 First (RTCmd:=10110-10111): these
commands control which of the two characters in a 16-bit
write to the TDR/TxFIFO the Transmitter sends first. They
also control how the channel arranges the oldest and
second-oldest characters in the RxFIFO when software or
an external Receive DMA controller reads 16 bits from the
Receive Data Register. “D15-8 First” is the default value
after either a hardware or programmed reset, and is
compatible with the Zilog Z8000, Zilog 16C0x and Motorola
680x0 processors. “D7-0 First” should be programmed for
the Zilog Z380 and most Intel processors. A channel
applies this option only during a 16-bit transfer, between
the TxFIFO or RxFIFO and the AD15-0 pins. However, if the
Transmit Character Counter contains 0001 and the Trans-
mit DMA controller writes 16 bits to the TxFIFO, the channel
only puts the character from AD7-0 in the TxFIFO, regard-
less of these commands. In a “D7-0 First” system this isn’t
a problem. But if the last character of a frame or message
falls at an even address when using the Transmit DMA
controller in a “D15-8 First” system, software must copy the
last character into the subsequent odd address as well.
UM009402-0201