Zilog Z16C30 - Manual (Page 76)

5-9
Z16C30 USC ®
U SER ' S M ANUAL Z ILOG
UM97USC0100
5.6 ASYNCHRONOUS MODE
Software can select classic asynchronous operation for
both the Transmitter and the Receiver, by programming
the TxMode and RxMode fields (CMR11-8 and CMR3-0
respectively) to 0000. The earlier Figure 5-1 shows how a
“0” Start bit precedes each character and a “Stop bit”
follows each, the latter being a “1” condition that’s more
than 1/2 bit time long. The idle state of the line is 1, and the
Transmitter and Receiver divide their input clocks by 16,
32, or 64 to arrive at the nominal bit time.
Software can make the Transmitter calculate and send a
parity bit with each character and can make the Receiver
check such parity bits, as described in the later section
Parity Checking.
The two more significant TxSubMode bits (CMR15-14)
control the minimum number of Stop bits that the Transmit-
ter sends between consecutive characters. The Transmit-
ter interprets them as follows:
CMR15-14 Minimum Length of Tx Stop
00 One bit time
01 Two bit times
10 One, “shaved” per CCR11-8
11 Two, “shaved” per CCR11-8
When CMR15 is 1 in this mode, the TxShaveL field of the
Channel Control Register (CCR11-8) controls the exact
length of the minimum Stop bit(s). If the 4-bit value in
TxShaveL is “n”, then the length of the shaved stop bit is
(n+1)/16-bit times. The following table summarizes the
stop bit possibilities afforded by CMR15-14 and CCR11-8:
Minimum Length of
CMR15-14 CCR11-8 Tx Stop
00 xxxx 1 bit time
01 xxxx 2 bit times
10 0000-0111 1/2 or less: DO NOT USE
10 1000 9/16
10 1001 5/8
10 1010-1110 11/16 to 15/16
10 1111 1 (as with CMR15-14=00)
11 0000 17/16
11 0001 9/8
11 0010-1110 19/16 to 31/16
11 1111 2 (as with CMR15-14=01)
The two LSbits of the Tx and RxSubMode fields (CMR13-
12 and 5-4) control the factors by which the Transmitter
and Receiver divide their TxCLK and RxCLK inputs to
arrive at the nominal bit length. A channel interprets both
fields as follows:
CMR13-12
& CMR5-4
Nominal Bit Length
00 TxClock or RxClock/16
01 TxClock or RxClock/32
10 TxClock or RxClock/64
11 Reserved, do not program
For the Receiver, choosing a larger divisor makes it sample
the data on RxD more often. This may result in a slightly
better error rate in marginal circumstances. For the Trans-
mitter there is no significance to the divisor chosen, other
than the convenience of choosing the same value as for the
Receiver, so that the same source can be used for both
RxCLK and TxCLK. (See Chapter 4 for more information
about clock selection.)
Zilog reserves the two MSbits of the RxSubMode field
(CMR7-6) in Asynchronous mode for use in future prod-
ucts. They should always be programmed as 00.
There is no such thing as a “received stop length” param-
eter: the Receiver does not expect or check for a particular
stop bit length. It simply samples the received data at the
nominal midpoint of a single Stop bit, and loads a corre-
sponding Framing Error bit into the RxFIFO with each
character. This bit migrates through the FIFO with its
associated character and eventually appears as the
CRCE/FE bit in the Receive Command/Status Register
(RCSR3). Note that RCSR3 can represent the status at the
time that a character marked with RxBound status was
read from the RxFIFO, or the status of the oldest 1 or 2
characters that are still in the RxFIFO, as described in the
later section 'Status Reporting'.
UM009402-0201