Zilog Z08470 - Manual (Page 121)

UM008007-0715 Z80 Instruction Description
Z80 CPU
User Manual
109
LD (nn), IY
Operation
(nn + 1) ← IYh, (nn) ← IYI
Op Code
LD
Operands
(nn), IY
Description
The low-order byte in Index Register IY is loaded to memory address (nn); the upper order
byte is loaded to memory location (nn + 1). The first n operand after the op code is the low-
order byte of nn.
Condition Bits Affected
None.
Example
If Index Register IY contains 4174h , then upon the execution of an LD ( 8838h ), IY
instruction, memory location 8838h contains 74h and memory location 8839h contains
41h .
M Cycles T States 4 MHz E.T.
6 20 (4, 4, 3, 3, 3, 3) 5.00
1 1 1 0 1 1 1 1 FD
0 0 0 1 0 0 1 0 22
n
n