Artesyn ATCA-8310 Installation and Use (May 2014) User Manual
Atca-8310
Advertising
This manual is related to the following products:
Table of contents
Document Outline
- ATCA-8310
- Contents
- About this Manual
- Introduction
- Hardware Preparation and Installation
- Controls, Indicators, and Connectors
- Functional Description
- 4.1 Block Diagram
- 4.2 Service and Packet Processor (SPP)
- 4.3 General Purpose Processor (GPP)
- 4.4 DSP Farm
- 4.5 Ethernet Network (ETH)
- 4.6 Timing Synchronization (TS)
- 4.7 Glue Logic FPGA
- 4.8 IPMC
- 4.9 Reset Structure
- BIOS
- 5.1 BIOS Considerations
- 5.2 BIOS Operation
- 5.3 Setup Utility
- 5.3.1 Main Menu
- 5.3.2 Advanced Menu
- 5.3.2.1 PCI Subsystem Sub-menu
- 5.3.2.2 ACPI Settings
- 5.3.2.3 Trusted Computing
- 5.3.2.4 S5 RTC Wake Settings
- 5.3.2.5 CPU Configuration
- 5.3.2.6 ME Configuration
- 5.3.2.7 Thermal Configuration
- 5.3.2.8 Port 80h
- 5.3.2.9 TDT Configurations
- 5.3.2.10 USB Configurations
- 5.3.2.11 AMT Configuration
- 5.3.2.12 Super IO Configuration
- 5.3.2.13 Serial Port Console Redirection
- 5.3.2.14 Network Stack
- 5.3.3 Chipset Menu
- 5.3.4 Boot Menu
- 5.3.5 Security Menu
- 5.3.6 Save Menu
- 5.4 Status Codes
- U-Boot
- 6.1 Overview
- 6.2 U-Boot
- 6.2.1 User Interface
- 6.2.1.1 Memory Map
- 6.2.1.2 Environment Variables
- 6.2.1.3 Network interfaces
- 6.2.1.4 GPP Control
- 6.2.1.5 Firmware Update
- 6.2.1.6 FPGA/Logic Operations
- 6.2.1.7 IPMI Interface
- 6.2.1.8 Application Boot
- 6.2.1.9 Default Boot Sequences
- 6.2.1.10 Broadcom Switch Configuration
- 6.2.1.11 Memory Initialization
- 6.2.1.12 SRIO Initialization
- 6.2.1.13 Miscellaneous Commands and Features
- 6.2.1.14 Power-on Self Test (POST)
- 6.2.1.15 Troubleshooting
- 6.2.1 User Interface
- Intelligent Peripheral Management Controller
- 7.1 IPMC Overview
- 7.2 Functional Overview
- 7.3 Firmware Architecture
- 7.4 HPM.1 Firmware Upgrade and Crisis Recovery
- 7.5 Sensors
- 7.6 Sensor Data Records
- 7.7 POST
- 7.8 FRU Inventory
- 7.9 Reset Domains and FRU Activation/Deactivation
- 7.10 U-Boot Boot Configuration Parameters
- 7.11 Asynchronous Event Notification
- 7.12 Serial Line Selection
- 7.13 Built-in Terminal Server
- 7.14 Fail Safe Logic and Watchdog Support
- 7.15 Payload Interface
- 7.16 Payload Boot Bank Selection
- 7.17 Settable Graceful Shutdown Timeout
- 7.18 FPGA Health Check
- 7.19 GPP THERMTRIP
- 7.20 Local System Event Log (SEL)
- 7.21 IPMI Hardware Watchdog
- 7.22 Artesyn OEM Command Set
- CPLD and FPGA
- 8.1 Power-up CPLD
- 8.2 Glue Logic FPGA
- 8.2.1 Glue Logic FPGA Architectural Overview
- 8.2.2 Registers
- 8.2.3 Logic Blocks
- 8.2.3.1 Telecom Clocking
- 8.2.3.2 Asynchronous Receiver Transmitter
- 8.2.3.3 Super IO Module
- 8.2.3.4 GPP Reset Controller
- 8.2.3.5 Watchdog Controller
- 8.2.3.6 GPP Interrupt Mapping Unit
- 8.2.3.7 SPP Interrupt Routing
- 8.2.3.8 Hardware Protection
- 8.2.3.9 Glue Logic FPGA Configuration Supervision
- 8.2.3.10 Glue Logic FPGA Dual Configuration
- 8.2.3.11 Communication between SPP, GPP and IPMC
- 8.2.3.12 SPP Failure Detection
- 8.2.3.13 SPP Persistent memory
- 8.2.3.14 SPI Interfaces DCM baseboard, DMC1, DMC2 and ARTM
- 8.2.3.15 Serial Redirection
- 8.2.3.16 Reset Domain Control
- 8.2.3.17 Miscellaneous
- 8.3 DSP FPGA
- 8.4 DSP FPGA HW/SW interfaces
- 8.4.1 DSP FPGA Address map Overview
- 8.4.2 DSP FPGA Registers Detailed Description
- 8.4.2.1 SerDes Client Interface (8bit each) (SerDesClientIf)
- 8.4.2.2 TSIP Interface Test Pattern Generator Block (TstPatGenBlk)
- 8.4.2.3 TSIP Interface Test Pattern Comparator Block ( TstPatCmpBlk)
- 8.4.2.4 TSIP to Serializer Converter Block (Tsip2SerBlk)
- 8.4.2.5 Deserializer to TSIP Allocater Block (Des2TsipBlk)
- 8.4.2.6 DSP Reset and NMI Control Block (DspResNmiCtrlBlk)
- 8.4.2.7 DSP Status and Interrupt Block (DspStaIntBlk)
- 8.4.2.8 DMC Power Supply Control Block (DmcPwrCtrlBlk)
- 8.4.2.9 General Registers (GnrlRegs)
- 8.4.2.10 Configuration Prom Update Registers (CfgPrmUpd)
- 8.4.2.11 General Test Registers (GenTestRegs)
- 8.4.2.12 I2C interface to Dsps (I2CIfToDsp)
- 8.4.2.13 MDIO interface to Phy (MdioIfToPhy)
- 8.4.3 Logic Blocks
- A Replacing the Battery
- B Related Documentation
- Safety Notes
- Sicherheitshinweise