Sundance SMT401 - Manual (Page 12)

Released Page 12 of 21 SMT401 PMC TIM Carrier User Guide
Document Name: SMT401 User Guide V1.2.doc Issue : 02 Rev.: 1.11
4 SMT401 Programming Registers
4.1 PCI Target Operation
In target mode, the SMT401 PMC is accessed by a host device across the
PCI bus. This allows access to the target mode registers. The operating
system or BIOS will normally allocate a base address for the target mode
registers of each SMT401 PMC. Access to each register within the SMT401
PMC is then specified by this base address and the offset shown in the table
below.
Offset Register(Write) Register(Read) Width
0 -
-
+4 - -
+8 - -
+0C - -
+10 COMPORT OUT COMPORT IN 32
+14 CONTROL STATUS 32
+18 INT CONTROL - 32
+1C - LAST PCI ADD 32
+20 to +3F Not used Not used
+40 to +7E Reserved Reserved 32
4.2 Comm-port Registers (Offset 10h)
The host is connected to the first TIM site using comm-port 3. This port is
bidirectional and will automatically switch direction to meet a request from
either the host or the C40. Both input and output registers are 32 bits wide.
Data should only be written to COMPORT_OUT when STATUS[OBF] is 0.
Data received from the C40 is stored in COMPORT_IN and STATUS[IBF] is
set to 1. Reading COMPORT_IN will clear STATUS[IBF] and allow another
word to be received from the C40.
4.2.1 Control Register (Offset 14h)
The CONTROL register can only be written. It contains flags which control
the boot modes of the first TIM site.
Boot Control
Bit 7-5 4 3 2 1 0
Name Not used notNMI IIOF2 IIOF1 IIOF0 RESET
RESET Write a 1 to this bit to assert the reset signal to all TIM modules on the SMT401
PMC.
IIOF0 IIOF1, IIOF2 These bits connect to the corresponding pins on the first TIM site. These bits are
open-drain and can only pull down. If not required before or after booting they should
be written with 1’s.
NotNMI A 0 written to this bit will assert the active low NMI to the TIM1 C40.
Note. On PCI system reset, RESET is asserted to all TIM sites.
Product Name: SMT401 Revision Date: 07 December 2004
Author: Mark I. Cartlidge (Updated by SM, added JTAG slave section) Original Date: 12 May 1999