Grass Valley 2020DAC D-To-A - Manual (Page 27)

2020DAC Instruction Manual 21
Functional Description
Digital Input
Either the balanced or unbalanced AES audio data is fed into the 2020DAC
through an isolation transformer to the receiver. The receiver extracts the
audio signal (left/right), as well as clock (bit clock, L/R clock and master
clock), sample rate, emphasis and error information. The signal, clock and
other decoded information is then passed to a FPGA (field-programmable
gate array) for further decoding and routing.
Control and Routing FPGA
The FPGA receives its programming and control information from the CPU
at power up. It also receives one of 16 output mode commands from a four-
bit rotary switch and the jumper configuration information. (Currently
only 13 of the settings are used.) The FPGA receives an AES stream from
the receiver and sends its outputs to the output DAC. The FPGA also per-
forms the following functions:
■ Decodes and drives the front panel LEDs,
■ Passes clock and audio information to the DAC for analog decoding,
■ Enables the appropriate emphasis filter for both channels for the
received sample rate on the DAC, and
■ Enables a soft mute that ramps up/down in about 20 ms (depending on
sample rate).
CPU (Controller)
The primary purpose of the CPU is to provide remote monitoring capa-
bility and local control for the 2020DAC. It receives information about:
■ Sample rate,
■ Emphasis,
■ Error,
■ Mode selection
■ Digital signal present, and
■ Output Level Range.
This information is passed through the frame controller to a remote moni-
toring location. A removable jumper is provided to allow disabling of
remote control.
The CPU configures the FPGA during boot-up. It also downloads software
updates as described in the 8900NET Module manual.