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Epson S1C6200 User Manual
Core cpu manual
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MF297-07
Core CPU Manual
CMOS 4-BIT SINGLE CHIP MICROCOMPUTER
S1C6200/6200A
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This manual is related to the following products:
S1C6200A
Table of contents
Document Outline
1 DESCRIPTION
1.1 System Features
1.2 Instruction Set Features
1.3 Differences between S1C6200 and S1C6200A
2 MEMORY AND OPERATIONS
2.1 Program Memory (ROM)
2.1.1 Program counter block
2.1.2 Flags
2.1.3 Jump instructions
2.1.4 PSET with jump instructions
2.1.5 Call instructions
2.1.6 PSET instruction
2.1.7 CALZ instruction
2.1.8 RET and RETS instructions
2.1.9 Stack considerations for call instructions
2.2 Data Memory
2.2.1 Data memory addressing
2.3 ALU (Arithmetic Logic Unit) and Registers
2.3.1 D (decimal) flag and decimal operations
2.3.2 A and B registers
2.4 Timing Generator
2.4.1 HALT and SLP (sleep) modes
2.5 Interrupts
2.5.1 Interrupt vectors
2.5.2 I (interrupt) flag
2.5.3 Operation during interrupt generation
2.5.4 Initial reset
3 INSTRUCTION SET
3.1 Instruction Indices
3.1.1 By function
3.1.2 In alphabetical order
3.1.3 By operation code
3.2 Operands
3.3 Flags
3.4 Instruction Types
3.5 Instruction Descriptions
APPENDIX
A. S1C6200A (ADVANCED S1C6200) CORE CPU
B. INSTRUCTION INDEX
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