Epson S1C6200 - Manual (Page 41)

Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
MSB LSB
MSB LSB
C –
Z –
D –
I –
C –
Z –
D –
I –
S1C6200/6200A CORE CPU MANUAL EPSON 35
3 INSTRUCTION SET
CP r,i
Compare immediate data i with r-register
CP r,i
r - i 3 to i 0
1 1 0 1 1 1 r 1 r 0 i 3 i 2 i 1 i 0 DC0H to DFFH
II
7
Set if r < i 3 to i 0 ; otherwise, reset.
Set if r = i
3
to i
0
; otherwise, reset.
Not affected
Not affected
Compares immediate data i to the r-register by subtracting i from the contents of r.
The r-register remains unchanged.
1. When Z = 0 and C = 0 then i < r
2. When Z = 1 and C = 0 then i = r
3. When Z = 0 and C = 1 then i > r
CP A,4 CP MX,7 CP B,2
A register 0100 0100 0100 0100
B register 1010 1010 1010 1010
Memory (MX) 0010 0010 0010 0010
C flag 1 0 1 0
Z flag 0 1 0 0
CP r,q Compare q-register with r-register
CP r,q
r - q
1 1 1 1 0 0 0 0 r
1
r
0
q
1
q
0
F00H to F0FH
IV
7
Set if r < q; otherwise, reset.
Set if r = q; otherwise, reset.
Not affected
Not affected
Compares the q-register to the r-register by subtracting the contents of q from the
contents of r. The registers remain unchanged.
1. When Z = 0 and C = 0 then q < r
2. When Z = 1 and C = 0 then q = r
3. When Z = 0 and C = 1 then q > r
CP A,B CP MY,A
A register 1000 1000 1000
B register 0100 0100 0100
Memory (MY) 0111 0111 0111
C flag 0 0 1
Z flag 0 0 0
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example: