Avago Technologies LSI53C876E User Manual
Page 121
SCSI Registers
4-27
following an expected SCSI disconnect. This bit is useful
for multithreaded applications. The ARB[1:0] bits in the
register are set for full
arbitration and selection before setting this bit.
Arbitration is retried until won. At that point, the
LSI53C876 SCSI function holds BSY and SEL asserted,
and waits for a select or reselect sequence. The
Immediate Arbitration bit is reset automatically when the
selection or reselection sequence is completed, or times
out. During the time between the assertion of the IARB
bit and the completion of a Perform Select/Reselect
instruction, DMA interrupts are disabled. Therefore,
interrupt instructions placed between the assertion of the
IARB bit and the Perform Select/Reselect instruction are
not executed.
An unexpected disconnect condition clears IARB without
attempting arbitration. See the SCSI Disconnect
Unexpected bit (
, bit 7) for
more information on expected versus unexpected
disconnects.
It is possible to abort an immediate arbitration sequence.
First, set the Abort bit in the
register. Then one of two things eventually happens:
•
The Won Arbitration bit (
,
bit 2) is set. In this case, the Immediate Arbitration bit
needs to be cleared. This completes the abort
sequence and disconnects the chip from the SCSI
bus. If it is not acceptable to go to Bus Free phase
immediately following the arbitration phase, it is
possible to perform a low level selection instead.
•
The abort completes because the LSI53C876 SCSI
function loses arbitration. This is detected by the
clearing of the Immediate Arbitration bit. Do not use
the Lost Arbitration bit (
bit 3) to detect this condition. In this case take no
further action.
SST
Start SCSI Transfer
0
This bit is automatically set during SCRIPTS execution. It
causes the SCSI core to begin a SCSI transfer, including
SREQ/SACK handshaking. The determination of whether
the transfer is a send or receive is made according to the